Abstract
With ever larger and more affordable storage capabilities, individuals and companies can now collect huge amounts of multimedia data, especially images. Searching such databases is still an open problem, known as content-based image retrieval (CBIR). In this paper, we present a hardware architecture based on FPGAs which aims at speeding-up visual CBIR.Our architecture is based on the unique combination of reconfigurable resources combined to Flash memory, and allows for a speed-up of 45 as compared to existing software solutions.
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Chikhi, R., Derrien, S., Noumsi, A., Quinton, P. (2007). Combining Flash Memory and FPGAs to Efficiently Implement a Massively Parallel Algorithm for Content-Based Image Retrieval. In: Diniz, P.C., Marques, E., Bertels, K., Fernandes, M.M., Cardoso, J.M.P. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2007. Lecture Notes in Computer Science, vol 4419. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-71431-6_23
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DOI: https://doi.org/10.1007/978-3-540-71431-6_23
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-71430-9
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