Abstract
In this paper we describe an FPGA implementation for solving Internet ranking algorithms. Sparse Matrix by Vector multiplication forms a major part of these algorithms. Due to memory bandwidth problems, general purpose processors only achieve a fraction of peak processing power when dealing with sparse matrices. Field-Programmable Gate Arrays (FPGAs) have the potential to significantly improve this performance. In order to support real life Internet ranking problems a large memory is needed to store the sparse matrix. This memory requirement cannot be fulfilled with the FPGA’s on-board block-RAM and SDRAM is expensive and limited in size. Commodity memory such as Double Data Rate (DDR) SDRAM is cheap and fully scalable and would appear to be the best solution. This paper discusses the possibility of a custom architecture on FPGA, for Internet ranking algorithms, using DDR SDRAM. An overview of work to date is also presented as well as a plan for future work.
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McGettrick, S., Geraghty, D., McElroy, C. (2007). Searching the Web with an FPGA Based Search Engine. In: Diniz, P.C., Marques, E., Bertels, K., Fernandes, M.M., Cardoso, J.M.P. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2007. Lecture Notes in Computer Science, vol 4419. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-71431-6_33
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DOI: https://doi.org/10.1007/978-3-540-71431-6_33
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