A New Low-Power and High Speed Viterbi Decoder Architecture

Abstract

In this paper, we propose a new architecture for low power and high speed viterbi decoder based on register exchange algorithm(RE). In general, the survivor memory unit (SMU) is adopted to RE method for viterbi decoder used in applications that require high speed and low latency. However, the look-ahead trace-back (LATB) method based on the RE method consumes much power due to the frequent switching -activities in register. In this paper, we propose a low power and high speed viterbi decoder that minimizes switching activities of the register used in LATB method to reduce power consumption of viterbi decoder. Because the trace bit of survivor path has a characteristic that the bit value converges into one of 0 or 1, we didn’t restore the trace bit to the register of the next stage but to that of the current stage. Simulation results show that the proposed low power and high speed viterbi decoder architecture can reduce switching activities by about 72% in comparison with the conventional LATB architecture using RE method when SNR is 5dB.