Abstract
The performance of existing adders varies widely in their speed and area requirements, which in turn sometimes makes designers pay a high cost in area especially when the delay requirements exceeds the fastest speed of a specific adder, no matter how small the difference is. To expand the design space and manage delay/area tradeoffs, we propose new adder architecture and a design methodology. The proposed adder architecture, named heterogeneous adder, decomposes an adder into blocks (sub-adders) consisting of carry-propagate adders of different types and precision. The flexibility in selecting the characteristics of sub-adders is the basis in achieving adder designs with desirable characteristics.
We consider the area optimization under delay constraints and the delay optimization under area constraints by determining the bit-width of sub-adders using Integer Linear Programming. We demonstrate the effectiveness of the proposed architecture and the design method on 128-bit operands.
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References
Nagendra, C., Irwin, M.J., Owens, R.M.: Area-time-power tradeoffs in parallel adders. IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing 43, 689–702 (1996)
Oklobdzija, V., Zeydel, B., Mathew, S., Krishnamurthy, R.: Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders. In: Proc. IEEE Symposium on Computer Arithmetic, Jun. 2003, pp. 272–279 (2003)
Wang, Y., Pai, C., Song, X.: The design of hybrid carry-lookahead/carry-select adders. IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing 49 (2002)
Oklobdzija, V., Villeger, D.: Improving Multiplier Design by Using Column Compression Tree and Optimized Final Adder in CMOS Technology. IEEE Trans. on VLSI 3(2), 292–301 (1995)
Stelling, P.F., Oklobdzija, V.: Design Strategies for Optimal Hybrid Final Adders in a Parallel Multiplier. Journal of VLSI Signal Processing 14(3), 321–331 (1996)
Ercegovac, M.D., Lang, T.: Digital Arithmetic. Morgan Kaufmann, San Francisco (2004)
Zimmermann, R.: Binary Adder Architectures for Cell-Based VLSI and their Synthesis. PhD thesis, Swiss Federal Institute of Technology (ETH) Zurich, Hartung-Gorre Verlag (1998)
Knowles, S.: A Family of Adders. In: Proc. IEEE Symposium on Computer Arithmetic, pp. 30–34 (1999)
Williams, H.P.: Model Building in Mathematical Programming, 4th edn. John Wiley, New York (1999)
Berkelaar, M.: lp_solve - version 4.0. Eindhoven University of Technology (2003), ftp://ftp.ics.ele.tue.nl/pub/lp_solve/
IDEC-C221: IDEC Cell Library Data Book. IC Design Education Center (2000)
DesignWare IP Family Reference Guide. Synopsis Corporation, September 12 (2005)
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Lee, JG., Lee, JA., Lee, BS., Ercegovac, M.D. (2007). A Design Method for Heterogeneous Adders. In: Lee, YH., Kim, HN., Kim, J., Park, Y., Yang, L.T., Kim, S.W. (eds) Embedded Software and Systems. ICESS 2007. Lecture Notes in Computer Science, vol 4523. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-72685-2_12
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DOI: https://doi.org/10.1007/978-3-540-72685-2_12
Publisher Name: Springer, Berlin, Heidelberg
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