Abstract
This paper presented a latency and power model to determine the bus configuration of a target SoC system at its early design stage. The latency model analyzed the latencies of an on-chip bus and provided throughput reflecting the bus configuration. The power model provided power estimation based on the pre-determined bus architecture. This paper showed new parameters to devise the proposed models such as bus usage, active bridge ratio, etc. Moreover, we evaluated the throughput of the bus and compared this with the required throughput of the target SoC, including a number of real IPs. This target SoC was configured based on the estimation results obtained from the proposed bus model. This estimation were compared with the simulation results of target SoC design for verifying the accuracy of the proposed model. The evaluation showed that the accuracies of the proposed model for the latency and the power model were over 85% and 92%, respectively. This result set the standard for an efficient bus structure for a SoC design.
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References
Cesario, W.O., Lyonnard, D., Nicolescu, G., Paviot, Y., Yoo, S., Jerraya, A.A., Gauthier, L., Diaz-Nava, M.: Multiprocessor SoC platforms:a component-based design approach. In: Design and Test of Computers, December 2002, vol. 19(6), pp. 52–63. IEEE Computer Society Press, Los Alamitos (2002)
Li, L., Gao, M., Cheng, Z., Zhang, D., He, S.: A new platform-based orthogonal SoC design methodology. In: Proc. 5th ASIC 2003, vol. 1(3) pp. 428–432 (2003)
Lahiri, K., Raghunathan, A.: Power analysis of system-level on-chip communication archi-tectures. In: Proc. Of CODES+ISSS 2004, pp. 236–241 (September 2004)
AMBA Specification Rev2.0, ARM co. (May 1999)
CoreConnect Bus Architecture, IBM Co. (1999)
Peterson, W.: WISHBONE: SoC Architecture Specification, Revision B.2, Silicore Co. (2001)
Lee, S.H., Lee, C.H., Lee, H.J.: A new multi-channel on-chip-bus architecture for system-on-chips. In: Proc. of IEEE International SOC Conference, pp. 305–308 (September 2004)
Ryu, K.K., Shin, E., Mooney, V.J.: A comparison of five different multiprocessor SoC bus architecture. In: Proc. of Euromicro Symposium on Digital Systems Design, pp. 202–209 (September 2001)
Okada, S., Takada, N., Miura, H., Asaeda, T.: System-on-a-chip for digital still camera with VGA-size clip shooting. IEEE Trans. On Consumer Electronics 46(3), 622–627 (2000)
Srinvasan, S., Li, L., Vijaykrishnan, N.: Simultaneous partitioning and frequency assign-ment for on-chip bus architecture. In: Proc. Design, Automation and Test in Europe, March 2005, vol. 1, pp. 213–218 (2005)
Zhang, Y., Ye, W., Irwin, M.J.: An alternative architecture for on-chip global intercon-nect: segmented bus power modeling. In: Proc. on ACSSC1998, vol. 2, pp. 1062–1065 (November 1998)
MaxSim developer suite user’s guide Ver 5.0, AXYS Design Automation Inc. (March 2004)
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Lee, JH., Cho, YS., Kim, SM., Cho, KR. (2007). On-Chip Bus Modeling for Power and Performance Estimation. In: Vassiliadis, S., Bereković, M., Hämäläinen, T.D. (eds) Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2007. Lecture Notes in Computer Science, vol 4599. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-73625-7_22
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DOI: https://doi.org/10.1007/978-3-540-73625-7_22
Publisher Name: Springer, Berlin, Heidelberg
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