Abstract
In this paper we present a general framework for the support of flexible models representation and execution in the context of SoC design space exploration. Coming as a C++ library, it allows the user to gather models from its own and existing models into larger and more complete models. Compared to existing modeling systems we introduce the notion of model reversibility that allows the user to turn any parameter appearing in a model into the output : it increases the model flexibility and enables its reuse in very different problems. Aside from providing specification and execution support, the framework also permits dynamic model sensitivity analysis and efficient parameter sensitivity analysis for closed-formed models. Through this paper we explain our original 3-level hierarchical representation of model and explain meanwhile how it offers flexibility and model robustness using a XML schema grammar.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Vincentelli, A.S.: Defining platform-based design. EEDesign of EETimes (2002)
Bossuet, L., Gogniat, G., Philippe, J.: Fast design space exploration method for reconfigurable architectures (2003)
Kahng, A.B.: Design technology productivity in the dsm era. In: Proc. Asia and South Pacific Design Automation Conf., pp. 443–448 (2001)
Robert, F.: How do we learn models? introducing the supposed range vs real range hypothesis. International Journal of Emerging Technologies in Learning 2(1) (2007)
VSIA: Vsia system level design model taxonomy document (2001)
Panagopoulos, I.: Models, specification languages and their interrelationship models, specification languages and their interrelationship for system level design. Technical report, HPCL,The George Washington University (2002)
Eker, J., Janneck, J.W., Lee, E.A., Liu, J., Liu, X., Ludvig, J., Neuendorffer, S., Sachs, S., Xiong, Y.: Taming heterogeneity - the ptolemy approach. Proceedings of the IEEE 91(1), 127–144 (2003)
SAE: Sae model specification process standard (2002)
Vachoux, A.: Méthodes et outils pour la modélisation de soc-ams. Technical report, EPFL, Lausanne (2002)
Codrescu, L., Nugent, S., Meindl, J., Wills, D.S.: Modeling technology impact on cluster microprocessor performance. IEEE Trans. Very Large Scale Integr. Syst. 11(5), 909–920 (2003)
Mangaser, R., Rose, K.: Facilitating interconnect-based vlsi design. In: MSE 1997. Proceedings of the 1997 International Conference on Microelectronics Systems Education, Washington, DC, p. 139. IEEE Computer Society Press, Los Alamitos (1997)
Sylvester, D., Keutzer, K.: System-level performance modeling with bacpac – berkeley advanced chip performance calculator (1999)
Caldwell, A.E., Cao, Y., Kahng, A.B., Koushanfar, F., Lu, H., Markov, I.L., Oliver, M., Stroobandt, D., Sylvester, D.: GTX: the MARCO GSRC technology extrapolation system. In: Design Automation Conference, pp. 693–698 (2000)
Sylvester, D., Keutzer, K.: Getting to the bottom of deep submicron ii: A global wiring paradigm (1999)
Redziejowski, R.R.: On arithmetic expressions and trees. Commun. ACM 12(2), 81–84 (1969)
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 2007 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Vander Biest, A., Richard, A., Milojevic, D., Robert, F. (2007). A Framework Introducing Model Reversibility in SoC Design Space Exploration. In: Vassiliadis, S., Bereković, M., Hämäläinen, T.D. (eds) Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2007. Lecture Notes in Computer Science, vol 4599. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-73625-7_23
Download citation
DOI: https://doi.org/10.1007/978-3-540-73625-7_23
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-73622-6
Online ISBN: 978-3-540-73625-7
eBook Packages: Computer ScienceComputer Science (R0)