Abstract
An integral part of FFT computation are the twiddle factors, which, in software implementations, are typically stored into RAM memory implying large memory footprint and power consumption. In this paper, we propose a novel twiddle factor generator based on reduced ROM tables. The unit supports both radix-4 and mixed-radix-4/2 FFT algorithms and several transform lengths. The unit operates at a rate of one factor per clock cycle.
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Pitkänen, T., Partanen, T., Takala, J. (2007). Low-Power Twiddle Factor Unit for FFT Computation. In: Vassiliadis, S., Bereković, M., Hämäläinen, T.D. (eds) Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2007. Lecture Notes in Computer Science, vol 4599. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-73625-7_9
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DOI: https://doi.org/10.1007/978-3-540-73625-7_9
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-73622-6
Online ISBN: 978-3-540-73625-7
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