Abstract
This paper provides a detailed investigation of latency penalties caused by repeated memory writes to nearby memory cells from different threads in parallel programs. When such writes map to the same corresponding cache lines in multiple processors, one can observe the so called false sharing effect. This effect can unnecessarily hamper parallel code due to the line granularity based cache hierarchy, which is common on contemporary processor architectures. In this contribution, a benchmark allowing for quantitative estimates about the consequences of the false sharing effect, is presented. Results show that multicore architectures with shared cache can reduce unwanted effects of false sharing.
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References
Intel Corporation: Intel 64 and IA-32 Architectures: Software Developer’s Manual, Denver, CO, USA (2006)
Torrellas, J., Lam, H.S., Hennessy, J.L.: False sharing and spatial locality in multiprocessor caches. IEEE Trans. Comput. 43(6), 651–663 (1994)
Papamarcos, M.S., Patel, J.H.: A low-overhead coherence solution for multiprocessors with private cache memories. In: ISCA 1998: 25 years of the international symposia on Computer architecture (selected papers), pp. 284–290. ACM Press, New York (1998)
Archibald, J., Baer, J.-L.: Cache coherence protocols: evaluation using a multiprocessor simulation model. ACM Trans. Comput. Syst. 4(4), 273–298 (1986)
Bolosky, W.J., Scott, M.L.: False sharing and its effect on shared memory performance. In: Proc. of the USENIX Symposium on Experiences with Distributed and Multiprocessor Systems (SEDMS IV), San Diego, CA, pp. 57–71 (1993)
Desikan, R., Burger, D., Keckler, S.W.: Sharing speculation: A mechanism for low-latency access to falsely shared data. Technical Report CS-TR-03-05, The University of Texas at Austin, Department of Computer Sciences, Friday, 11 August, 106 16:16:41 GMT (2003)
Liu, K.C., King, C.T.: On the effectiveness of sectored caches in reducing false sharing misses. In: International Conference on Parallel and Distributed Systems (ICPADS ’97), December 11-13, 1997, Seoul, Korea, Proceedings, pp. 352–359 (1997)
Kadiyala, M., Bhuyan, L.N.: A dynamic cache sub-block design to reduce false sharing. In: ICCD 1995. Proceedings of the 1995 International Conference on Computer Design, Washington, DC, USA, p. 313. IEEE Computer Society Press, Los Alamitos (1995)
Sweazey, P., Smith, A.J.: A class of compatible cache consistency protocols and their support by the ieee futurebus. In: ISCA 1986. Proceedings of the 13th annual international symposium on Computer architecture, pp. 414–423. IEEE Computer Society Press, Los Alamitos (1986)
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Weidendorfer, J., Ott, M., Klug, T., Trinitis, C. (2007). Latencies of Conflicting Writes on Contemporary Multicore Architectures. In: Malyshkin, V. (eds) Parallel Computing Technologies. PaCT 2007. Lecture Notes in Computer Science, vol 4671. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-73940-1_33
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DOI: https://doi.org/10.1007/978-3-540-73940-1_33
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-73939-5
Online ISBN: 978-3-540-73940-1
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