Abstract
In VLIW processor design, clustered architecture becomes a popular solution for better hardware efficiency. But the inter-cluster communication (ICC) will cause the execution cycles overhead. In this paper, we propose a shared cluster register file (SCRF) architecture and a SCRF register allocation algorithm to reduce the ICC overhead. The SCRF architecture is a hybrid register file (RF) organization composed of shared RF (SRF) and clustered RFs (CRFs). By putting the frequently used variables that need ICCs on SRF, we can reduce the number of data communication of clusters and thus reduce the ICC overhead. The SCRF register allocation algorithm exploits this architecture feature to perform optimization on ICC reduction and spill codes balancing. The SCRF register allocation algorithm is a heuristic based on graph coloring. To evaluate the performance of the proposed architecture and the SCRF register allocation algorithm, the frequently used two-cluster architecture with and without the SRF scheme are simulated on Trimaran. The simulation results show that the performance of the SCRF architecture is better than that of the clustered RF architecture for all test programs in all measured metrics.
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References
Aleta, A., Condina, J.M., Gonzalez, A., Kaeli, D.: Removing Communications in Clustered Microarchitectures through Instruction Replication. ACM Trans. Arch. and Code Opt. 1, 127–151 (2004)
Gibert, E., Sanchez, J., Gonzalez, A.: Distributed Data Cache Designs for Clustered VLIW Processors. IEEE Trans. Computers 54, 1227–1241 (2005)
Parcerisa, J.M., Sahuquillo, J., Gonzalez, A., Duato, J.: On-chip Interconnects and Instruction Steering Schemes for Clustered Microarchitectures. IEEE Trans. Parallel and Distributed Systems 16, 130–144 (2005)
Terechko, A., Garg, M., Corporaal, H.: Evaluation of Speed and Area of Clustered VLIW Processors. In: Proc. 18th Int. Conf. VLSI Design, pp. 557–563 (2005)
Gangwar, A., Balakrishnan, M., Kumar, A.: Impact of Inter-cluster Communication Mechanisms on ILP in Clustered VLIW Architectures. In: 2nd Workshop on Application Specific Processors, in conj. 36th IEEE/ACM Annual Int. Symp. Microarchitecture (2003)
Lin, Y.-C., You, Y.-P., Lee, J.-K.: Register Allocation for VLIW DSP Processors with Irregular Register Files. In: Proc. Compilers for Parallel Computers, pp. 45–59 (2006)
Nagpal, R., Srikant, Y.N.: Integrated Temporal and Spatial Scheduling for Extended Operand Clustered VLIW Processors. In: Proc. 1st Conf. Computing Frontiers, pp. 457–470 (2004)
Zalamea, J., Llosa, J., Ayguade, E., Valero, M.: Hierarchical Clustered Register File Organization for VLIW Processors. In: Proc. 17th Int. Symp. Parallel and Distributed Processing, p. 77.1 (2003)
Zhang, Y., He, H., Sun, Y.: A New Register File Access Architecture for Software Pipelining in VLIW Processors. In: Proc. Conf. Asia and South Pacific Design Automation, vol. 1, pp. 627–630 (2005)
Terechko, A., Le Thenaff, E., Corporaal, H.: Cluster Assignment of Global Values for Clustered VLIW Processors. In: Proc. Int. Conf. Compilers, Architecture and Synthesis for Embedded Systems, pp. 32–40 (2003)
Chaitin, G.J.: Register allocation and spilling via graph coloring. In: Proc. ACM SIGPLAN Symp. Compiler Construction, pp. 98–105 (1982)
Trimaran Consortium: The Trimaran Compiler Infrastructure (1998), http://www.trimaran.org
CCCP research group: Compilers Creating Custom Processors, http://cccp.eecs.umich.edu
Lee, C., Potkonjak, M., Mangione-Smith, W.H.: MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems. In: Proc. 30th ACM/IEEE Int. Symp. Microarchitecture, pp. 330–350 (1997)
Ellis, J.: Bulldog: A Compiler for VLIW Architectures. MIT Press, Cambridge (1985)
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Hsu, JY., Wu, YZ., Lin, XY., Chung, YC. (2007). SCRF – A Hybrid Register File Architecture. In: Malyshkin, V. (eds) Parallel Computing Technologies. PaCT 2007. Lecture Notes in Computer Science, vol 4671. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-73940-1_52
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DOI: https://doi.org/10.1007/978-3-540-73940-1_52
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