Performance Optimization of Embedded Applications in a Hybrid Reconfigurable Platform

Abstract

This work presents an extensive study on the speedups achieved by mapping real-life applications in different instances of a hybrid reconfigurable system. The embedded heterogeneous system is composed by reconfigurable hardware units of different granularity. The fine-grain reconfigurable logic is realized by an FPGA, while the coarse-grain reconfigurable hardware by a 2-Dimensional array of word-level Processing Elements. Performance gains are achieved by mapping time critical loops, which execute slowly on the FPGA, on the Coarse-Grain Reconfigurable Array. An automated design flow was developed for mapping applications on the reconfigurable units of the platform. The conducted experiments illustrate that the speedups relative to an all-FPGA execution range from 2.33 to 6.42 being close to theoretical speedup bounds.