Abstract
This paper investigates the use of the Logarithmic Number System (LNS) as a low-power design technique for signal processing applications. In particular we focus on power reductions in implementations of FIR and IIR filters. It is shown that LNS requires a reduced word length compared to linear representations for cases of practical interest. Synthesis of circuits that perform basic arithmetic operations using a 0.18μm 1.8V CMOS standard-cell library, reveal that power dissipation savings more than 60% in some cases are possible.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
Stouraitis, T., Paliouras, V.: Considering the alternatives in low-power design. IEEE Circuits and Devices 17, 23–29 (2001)
Landman, P.E., Rabaey, J.M.: Architectural power analysis: The dual bit type method. IEEE Transactions on VLSI Systems 3, 173–187 (1995)
Arnold, M.G., Bailey, T.A., Cowles, J.R., Winkel, M.D.: Applying features of the IEEE 754 to sign/logarithm arithmetic. IEEE Transactions on Computers 41, 1040–1050 (1992)
Morley, J. R.E., Engel, G.L., Sullivan, T.J., Natarajan, S.M.: VLSI based design of a battery-operated digital hearing aid. In: Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing, 1988, pp. 2512–2515. IEEE Computer Society Press, Los Alamitos (1988)
Sacha, J.R., Irwin, M.J.: Number representation for reducing switched capacitance in subband coding. In: Proceedings of IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 1998, pp. 3125–3128 (1998)
Arnold, M.G.: Reduced power consumption for mpeg decoding with lns. In: Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2002), IEEE Computer Society Press, Los Alamitos (2002)
Kang, B., Vijaykrishnan, N., Irwin, M.J., Theocharides, T.: Power-efficient implementation of turbo decoder in sdr system. In: Proceedings of the IEEE International SOC Conference, pp. 119–122 (2004)
Paliouras, V., Stouraitis, T.: Low-power properties of the Logarithmic Number System. In: Proceedings of 15th Symposium on Computer Arithmetic (ARITH15), Vail, CO, June 2001, pp. 229–236 (2001)
Paliouras, V., Stouraitis, T.: Logarithmic number system for low-power arithmetic. In: Soudris, D.J., Pirsch, P., Barke, E. (eds.) PATMOS 2000. LNCS, vol. 1918, pp. 285–294. Springer, Heidelberg (2000)
Taylor, F., Gill, R., Joseph, J., Radke, J.: A 20 bit Logarithmic Number System processor. IEEE Transactions on Computers 37, 190–199 (1988)
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 2007 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Basetas, C., Kouretas, I., Paliouras, V. (2007). Low-Power Digital Filtering Based on the Logarithmic Number System. In: Azémard, N., Svensson, L. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2007. Lecture Notes in Computer Science, vol 4644. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-74442-9_53
Download citation
DOI: https://doi.org/10.1007/978-3-540-74442-9_53
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-74441-2
Online ISBN: 978-3-540-74442-9
eBook Packages: Computer ScienceComputer Science (R0)