Abstract
In this paper, a power efficient 2K asynchronous SRAM is presented for embedded applications. The SRAM adopts a low swing write scheme, which greatly reduces the power dissipated by charging and discharging the bitlines. A small dual-rail decoder is proposed to compensate for the extra silicon area needed by the low swing write technique. The new SRAM is demonstrated to a factor of 4 improvement in power efficiency over a commercial SRAM macro. It also 30% faster than the commercial SRAM macro with only 3% area overhead.
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Liu, Y., Chen, P., Wang, W., Li, Z. (2007). The Design and Implementation of a Power Efficient Embedded SRAM. In: Azémard, N., Svensson, L. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2007. Lecture Notes in Computer Science, vol 4644. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-74442-9_9
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DOI: https://doi.org/10.1007/978-3-540-74442-9_9
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-74441-2
Online ISBN: 978-3-540-74442-9
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