Abstract
Register file design is very important in high performance processor design. Register Stack and Register Rotation are effective ways to improve performance. Compiler optimizations are often driven by specific assumptions about the underlying architecture and implementation of the target machine. SMT(simultaneous multithreading) processors execute instructions from different threads in the same cycle, which has the unique ability to exploit ILP(instruction-level parallelism) and TLP(thread-level parallelism) simultaneously. EPIC(explicitly parallel instruction computing) emphasizes importance of the synergy between compiler and hardware. In this paper, we present our efforts to design and implement register file management mechanism on a parallel environment, which includes an optimizing, portable parallel compiler OpenUH and SMT architecture EDSMT based on IA-64. Meanwhile, its compile optimization is also considered to improve the performance.
This work was supported by “863” project No. 2002AA110020, Chinese NSF No. 60376018, No. 60273069 and No. 90207011.
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Deng, Q., Zhang, M., Jiang, J. (2007). Register File Management and Compiler Optimization on EDSMT. In: Thulasiraman, P., He, X., Xu, T.L., Denko, M.K., Thulasiram, R.K., Yang, L.T. (eds) Frontiers of High Performance Computing and Networking ISPA 2007 Workshops. ISPA 2007. Lecture Notes in Computer Science, vol 4743. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-74767-3_41
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DOI: https://doi.org/10.1007/978-3-540-74767-3_41
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