Abstract
In this paper we consider a high-level hardware description language Gezel, from which hardware can be synthesized through a translation to VHDL. The language is equipped with a simulator and supports exploration of hardware designs. The language has no semantics and it is difficult to get a deep understanding of many of the constructions. We therefore give a semantic domain for Gezel. Aiming at automated verification we relate this domain to the timed-automata model and we have experimented with verification of Gezel-specifications using the Uppaal system. In particular, we have proven the correctness of a hardware specification of the Simplified DES algorithm. We have also used Uppaal for small experiments of verifying resource usage.
This work has been partially funded by The Danish Council for Strategic Research under project MoDES, the Danish National Advanced Technology Foundation under project DaNES, and ARTIST2 (IST-004527).
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Hansen, M.R., Madsen, J., Brekling, A.W. (2007). Semantics and Verification of a Language for Modelling Hardware Architectures. In: Jones, C.B., Liu, Z., Woodcock, J. (eds) Formal Methods and Hybrid Real-Time Systems. Lecture Notes in Computer Science, vol 4700. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-75221-9_13
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DOI: https://doi.org/10.1007/978-3-540-75221-9_13
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