Abstract
The SANE Virtual Processor (SVP) is a fine-grain, thread-based model of concurrent program composition developed and used at the University of Amsterdam as a basis for designing and programming many-core chips. Its design goal was to support dynamic concurrency and hence support self-adaptive systems within the AETHER collaborative European project. It provides an effective solution for programming chip multiprocessor systems [1,2,3]. In this paper, we take thread algebra [4], a semantics for recent object-oriented programming languages such as C# and Java, as a theoretical framework to the verification and evaluation of SVP. We show how a SVP program behavior can be determined in \({\textnormal{TA}_{\it svp}}\), an extension of thread algebra with the features of SVP, and prove that SVP programs satisfy the determinism property, i.e. the programs always give the same result, a key property of the sequential paradigm that SVP will replace.
The work presented in this paper is supported by NWO (Netherlands Organisation for Scientific Research) in the “Foundations for Massively Parallel on-chip Architectures using Microthreading” project.
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References
Bolychevsky, A., Jesshope, C., Muchnick, V.: Dynamic sheduling in rics architectures. IEE Proceedings Computers and Digital Techniques 143(5), 309–317 (1996)
Bousias, K., Hasasneh, N., Jesshope, C.: Instruction-level parallelism through Microthreading-a scalable Approach to chip multiprocessors. The Computer Journal 49 (2), 211–233 (2006)
Jesshope, C.: Microthreading a model for distributed instruction-level concurrency. Parallel Processing Letters 16 (2), 209–228 (2006)
Bergstra, J., Middelburg, C.: Thread algebra for strategic interleaving. Formal Aspects of Computing. Preliminary version: Computer Science Report PRG0404: Sectie Software Engineering, University of Amsterdam (to appear, 2007)
Jesshope, C., Luo, B.: Micro-threading: A new approach to future risc. In: ACAC 2000, pp. 31–41. IEEE Computer Society Press, Los Alamitos (2000)
Jesshope, C.: Multithreaded microprocessors evolution or revolution. In: Omondi, A.R., Sedukhin, S. (eds.) ACSAC 2003. LNCS, vol. 2823, pp. 21–45. Springer, Heidelberg (2003)
Bergstra, J., Middelburg, C.: Maurer computers with single-thread control. Fundamenta Informaticae (to appear, 2007)
Maurer, W.: A theory of computer instructions. Journal of ACM 13(2), 226–235 (1966)
Maurer, W.: A theory of computer instructions. Science of Computer Programming 55(1/2), 1–19 (2006)
Hopcroft, J., Motwani, R., Ullman, J.: Introduction to Automata Theory, Languages and Computation, 2nd edn. Addition-Wesley, Reading, MA (2001)
Bergstra, J., Middelburg, C.: Simulating turing machines on maurer machines. CS-Report 05-28, Department of mathematics and computer science, Technische Universiteit Eindhoven (2005)
Bergstra, J., Middelburg, C.: Maurer computers for pipelined instruction processing. CS-Report 06-12, Department of mathematics and computer science, Technische Universiteit Eindhoven (2006)
Bergstra, J., Middelburg, C.: Synchronous cooperation for explicit multi-threading. CS-Report 06-29, Department of mathematics and computer science, Technische Universiteit Eindhoven (2006)
Vu, T., Jesshope, C.: Thread algebra for SANE virtual processors (2007), available at http://staff.science.uva.nl/~jesshope
Jesshope, C.: SVP and μTC-A dynamic model of concurrency and its implementation as a compiler target (2006), http://staff.science.uva.nl/~jesshope/Papers/uTC-paper.pdf
Bergstra, J., Loots, M.: Program algebra for sequential code. J. of Logic and Algebraic Programming 51, 125–156 (2002)
Baeten, J., Bergstra, J.: Process algebra with signals and conditions. In: Broy, M. (ed.) Programming and Mathematical Methods. NATO ASI Series, vol. F88, pp. 1–21 (1992)
Milner, R.: Communication and Concurrency. Prentice-Hall, Englewood Cliffs (1989)
Bergstra, J., Klop, J.: Process algebra for synchronous communication. Inform. and Control 60 (1-3), 109–137 (1984)
Ungerer, T., Robič, B., Šilc, J.: A survey of processors with explicit multithreading. ACM Computing Surveys 35 (1), 29–63 (2003)
Fokkink, W.: Introduction to Process Algebra. EATCS Series. Springer, Heidelberg (2000)
Bakker, J., Zucker, J.: Processes and the denotational semantics of concurrency. Information and Control 54(1/2), 70–120 (1982)
Plotkin, G.: A structural approach to operational semantics. Aarhus DAIMI FN-19, Computing Science Department (1981)
Aceto, L., Fokkink, W., Verhoef, C.: Structural operational semantics. In: Bergstra, J., Ponse, A., Smolka, S. (eds.) Handbook of Process Algebra, pp. 197–222. Elsevier, Amsterdam (2001)
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Vu, T.D., Jesshope, C. (2007). Formalizing SANE Virtual Processor in Thread Algebra. In: Butler, M., Hinchey, M.G., Larrondo-Petrie, M.M. (eds) Formal Methods and Software Engineering. ICFEM 2007. Lecture Notes in Computer Science, vol 4789. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-76650-6_20
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DOI: https://doi.org/10.1007/978-3-540-76650-6_20
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