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International Conference on Cryptology in India

INDOCRYPT 2007: Progress in Cryptology – INDOCRYPT 2007 pp 373–383Cite as

Design of a Differential Power Analysis Resistant Masked AES S-Box

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Part of the book series: Lecture Notes in Computer Science ((LNSC,volume 4859))

Abstract

Gate level masking is one of the most popular countermeasures against Differential Power Attack (DPA). The present paper proposes a masking technique for AND gates, which are then used to build a balanced and masked multiplier in GF(2n). The circuits are shown to be computationally secure and have no glitches which are dependent on unmasked data. Finally, the masked multiplier in GF(24) is used to implement a masked AES S-Box in GF(24)2. Power measurements are taken to support the claim of random power consumption.

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Author information

Authors and Affiliations

  1. MTech Student, Department of Computer Science and Engg., Indian Institute of Technology, Kharagpur, India

    Kundan Kumar

  2. Assistant Professor, Department of Computer Science and Engg., Indian Institute of Technology, Madras, India

    Debdeep Mukhopadhyay

  3. Professor, Department of Computer Science and Engg., Indian Institute of Technology, Kharagpur, India

    Dipanwita RoyChowdhury

Authors
  1. Kundan Kumar
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  2. Debdeep Mukhopadhyay
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  3. Dipanwita RoyChowdhury
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Editor information

K. Srinathan C. Pandu Rangan Moti Yung

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Kumar, K., Mukhopadhyay, D., RoyChowdhury, D. (2007). Design of a Differential Power Analysis Resistant Masked AES S-Box. In: Srinathan, K., Rangan, C.P., Yung, M. (eds) Progress in Cryptology – INDOCRYPT 2007. INDOCRYPT 2007. Lecture Notes in Computer Science, vol 4859. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-77026-8_29

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  • DOI: https://doi.org/10.1007/978-3-540-77026-8_29

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-77025-1

  • Online ISBN: 978-3-540-77026-8

  • eBook Packages: Computer ScienceComputer Science (R0)

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