Abstract
This paper proposes a cost-effective VLSI architecture to improve the three-step search (TSS) algorithm for efficient motion estimation. A weighted SAD is defined as the new distortion measure instead of SAD for motion vector selection to remedy the fault of the TSS algorithm. The proposed TSS architecture is superior to conventional TSS architecture in terms of coding performance. Moreover, the additional hardware implementation cost of the proposed architecture is relatively negligible. The proposed architecture achieves best tradeoff in terms of speed and hardware cost.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Chen, T.-C., Chien, S.-Y., Huang, Y.-W., Tsai, C.-H., Chen, C.-Y., Chen, T.-W., Chen, L.-G.: Analysis and Architecture Design of an HDTV720p 30 Frames/s H.264/AVC Encoder. IEEE Trans. Circuits Syst. Video Technol., 166 (June 2006)
Tuan, J.-C., Chang, T.-S., Jen, C.-W.: On the Data Reuse and Memory Bandwidth Analysis for Full-Search Block-Matching VLSI Architecture. IEEE Trans. Circuits Syst. Video Technol., 121 (January 2002)
Jong, H.-M., Chen, L.-G., Chiueh, T.-D.: Accuracy improvement and cost reduction of 3-step search block-matching algorithm for video coding. IEEE Trans. Circuits Syst. Video Technol., 4(1), 88–90 (1994)
Chen, T.H.: A cost-effective three-step hierarchical search block-matching chip for motion estimation. IEEE Journal of Solid-State Circuits 338, 1253–1258 (1998)
Yin, H.B., Fang, X.Z., Yang, H., Yu, S.Y., Yang, X.K.: Motion Vector Smoothing for True Motion Estimation. In: IEEE Conference on Acoustics, Speech and Signal Processing 2006 p. II-241–II-244 (2006)
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 2007 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Yin, H.B., Xia, Z.L., Lou, X.Z. (2007). An Improved Three-Step Hierarchical Motion Estimation Algorithm and Its Cost-Effective VLSI Architecture. In: Ip, H.HS., Au, O.C., Leung, H., Sun, MT., Ma, WY., Hu, SM. (eds) Advances in Multimedia Information Processing – PCM 2007. PCM 2007. Lecture Notes in Computer Science, vol 4810. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-77255-2_98
Download citation
DOI: https://doi.org/10.1007/978-3-540-77255-2_98
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-77254-5
Online ISBN: 978-3-540-77255-2
eBook Packages: Computer ScienceComputer Science (R0)