Abstract
Multiple clock domain (MCD) chip design addresses the problem of increasing clock skew in different chip units. Importantly, MCD design offers an opportunity for fine grain power/energy management of the components in each clock domain with dynamic voltage scaling (DVS). In this paper, we propose and evaluate a novel integrated DVS approach to synergistically manage the energy of chip components in different clock domains. We focus on embedded processors where core and L2 cache domains are the major energy consumers. We propose a policy that adapts clock speed and voltage in both domains based on each domain’s workload and the workload experienced by the other domain. In our approach, the DVS policy detects and accounts for the effect of inter-domain interactions. Based on the interaction between the two domains, we select an appropriate clock speed and voltage that optimizes the energy of the entire chip. For the Mibench benchmarks, our policy achieves an average improvement over no-power-management of 15.5% in energy-delay product and 19% in energy savings. In comparison to a traditional DVS policy for MCD design that manages domains independently, our policy achieves an 3.5% average improvement in energy-delay and 4% less energy, with a negligible 1% decrease in performance. We also show that an integrated DVS policy for MCD design with two domains is more energy efficient for simple embedded processors than high-end ones.
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References
National Semiconductor, PowerWise Technology (2007), http://www.national.com/appinfo/power/powerwise.html
Magklis, G., Semeraro, G., Albonesi, D.H., Dropsho, S.G., Dwarkadas, S., Scott, M.L.: Dynamic Frequency and Voltage Scaling for a Multiple-Clock-Domain Microprocessor. IEEE Micro 23(6), 62–68 (2003)
Semeraro, G., Albonesi, D.H., Dropsho, S.G., Magklis, G., Dwarkadas, S., Scott, M.L.: Dynamic frequency and voltage control for a multiple clock domain microarchitecture. In: MICRO 1935. Proc Intl Symp on Microarchitecture, pp. 356–367 (2002)
Iyer, A., Marculescu, D.: Power and performance evaluation of globally asynchronous locally synchronous processors. In: ISCA 2002. Proc Intl Symp on Computer architecture, pp. 158–168 (2002)
Magklis, G., Scott, M.L., Semeraro, G., Albonesi, D.H., Dropsho, S.: Profile-based dynamic voltage and frequency scaling for a multiple clock domain microprocessor. In: ISCA 2003. Proc Intl Symp on Computer Architecture, pp. 14–27 (2003)
Wu, Q., Juang, P., Martonosi, M., Clark, D.W.: Formal online methods for voltage/frequency control in multiple clock domain microprocessors. In: ASPLOS-XI. Proc Intl Conf on Architectural support for programming languages and operating systems, pp. 248–259 (2004)
Ben Naser, M., Moritz, C.A.: A Step-by-Step Design and Analysis of Low Power Caches for Embedded Processors (2005), http://www.lems.brown.edu/iris/BARC2005/Webpage/BARCpresentations/ben-naser.pdf
Kaxiras, S., Hu, Z., Martonosi, M.: Cache decay: exploiting generational behavior to reduce cache leakage power. In: ISCA 2001. Proc Intl Symp on Computer Architecture, pp. 240–251 (2001)
Zhu, Y., Albonesi, D.H., Buyuktosunoglu, A.: A High Performance, Energy Efficient GALS Processor Microarchitecture with Reduced Implementation Complexity. In: ISPASS 2005. Proc Intl Symp on Performance Analysis of Systems and Software (2005)
SimpleScalar/ARM. SimpleScalar-Arm Version 4.0 Test Releases, http://www.simplescalar.com/v4test.html/
Intel Embedded products. High-Performance Energy-Efficient Processors for Embedded Market Segments (2006), http://www.intel.com/design/embedded/downloads/315336.pdf
Pennanen, J.: Optimizing the Power for Multiple Voltage Domains. Spring Processor Forum, Japan (2006)
Rusu, C., AbouGhazaleh, N., Ferreria, A., Xu, R., Childers, B., Melhem, R., Mossé, D.: Integrated CPU and L2 cache Frequency/Voltage Scaling using Supervised Learning. In: Workshop on Statistical and Machine learning approaches applied to ARchitectures and compilation (SMART) (2007)
AbouGhazaleh, N., Ferreria, A., Rusu, C., Xu, R., Childers, B., Melhem, R., Mossé, D.: Integrated CPU and L2 cache Voltage Scaling using Supervised Learning. In: LCTES 2007. Proc. of ACM SIGPLAN on Language, compiler, and tool for embedded systems (2007)
Wu, Q., Juang, P., Martonosi, M., Clark, D.W.: Voltage and Frequency Control With Adaptive Reaction Time in MCD Processors. In: HPCA 2005: Proc Intl Symp on High-Performance Computer Architecture, pp. 178–189 (2005)
Oliver, J., Rao, R., Sultana, P., Crandall, J., Czernikowski, E., Jones IV, L.W., Franklin, D., Akella, V., Chong, F.T.: Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor. In: ISCA 2004. Proc Intl Symp on Computer Architecture (2004)
Juang, P., Wu, Q., Peh, L.S., Martonosi, M., Clark, D.W.: Coordinated, distributed, formal energy management of chip multiprocessors. In: ISLPED 2005: Proc Intl Symp on Low Power Electronics and Design, pp. 127–130 (2005)
Lopez, S., Dropsho, S., Albonesi, D., Garnica, O., Lanchares, J.: Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches. In: High Performance Embedded Architecure and Compilation (HiPEAC) (2007)
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AbouGhazaleh, N., Childers, B., Mossé, D., Melhem, R. (2008). Integrated CPU Cache Power Management in Multiple Clock Domain Processors. In: Stenström, P., Dubois, M., Katevenis, M., Gupta, R., Ungerer, T. (eds) High Performance Embedded Architectures and Compilers. HiPEAC 2008. Lecture Notes in Computer Science, vol 4917. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-77560-7_15
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DOI: https://doi.org/10.1007/978-3-540-77560-7_15
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