Abstract
This paper describes the acceleration of calculations for public-key cryptography on hyperelliptic curves on very small FPGAs. This is achieved by using a Hardware/Software Codesign Approach starting with an all-software implementation on an embedded Microprocessor and migrating very time-consuming calculations from software to hardware. Basic GF(2n)-hardware extensions are connected to work in conjunction with the Microprocessor and possible alternatives for connecting external hardware to the Microprocessor are investigated. The performance of the hardware implementations compared to their counterparts as a software approach are evaluated. Based on these results, a coprocessor is devised and optimized for performance. The system utilizes minimal resources and fits easily on a small FPGA. It allows for fast Hyperelliptic Curve Cryptography (HECC) operations while running at a very low clock speed of 33 MHz, thus making it suitable for usage in embedded systems.
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Klimm, A., Sander, O., Becker, J., Subileau, S. (2008). A Hardware/Software Codesign of a Co-processor for Real-Time Hyperelliptic Curve Cryptography on a Spartan3 FPGA. In: Brinkschulte, U., Ungerer, T., Hochberger, C., Spallek, R.G. (eds) Architecture of Computing Systems – ARCS 2008. ARCS 2008. Lecture Notes in Computer Science, vol 4934. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-78153-0_15
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DOI: https://doi.org/10.1007/978-3-540-78153-0_15
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