Abstract
Recently Network-on-Chip (NoC) technique has been proposed as a promising solution for on-chip interconnection network. However, different interface specification of integrated components raises a considerable difficulty for adopting NoC techniques. In this paper, we present a generic architecture for network interface (NI) and associated wrappers for a networked processor array (NoC based multiprocessor SoC) in order to allow systematic design flow for accelerating the design cycle. Case studies for memory and turbo decoder IPs show the feasibility and efficiency of our approach.
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Lee, S.E., Bahn, J.H., Yang, Y.S., Bagherzadeh, N. (2008). A Generic Network Interface Architecture for a Networked Processor Array (NePA). In: Brinkschulte, U., Ungerer, T., Hochberger, C., Spallek, R.G. (eds) Architecture of Computing Systems – ARCS 2008. ARCS 2008. Lecture Notes in Computer Science, vol 4934. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-78153-0_19
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DOI: https://doi.org/10.1007/978-3-540-78153-0_19
Publisher Name: Springer, Berlin, Heidelberg
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