Synthesizing FPGA Circuits from Parallel Programs

Abstract

In this presentation we describe recent experiments to represent circuit descriptions as explicit parallel programs written in regular programming languages rather than hardware description languages. Although there has been much work on compiling sequential C-like programs to hardware by automatically “discovering” parallelism we work by exploiting the parallel architecture communicated by the designer through the choice of parallel and concurrent programming language constructs. Specially, we describe a system that takes .NET assembly language with suitable custom attributes as input and produces Verilog output which is mapped to FPGAs. We can then choose to apply analysis and verification techniques to either the high level representation in C# or other .NET languages or to the generated RTL netlisits.