Abstract
This paper explores the application of reconfigurable hardware to the acceleration of financial computations involving binomial-tree pricing models. A parallel pipelined architecture capable of computing multiple binomial trees is presented, which can deal with concurrent requests for option valuations. The architecture is mapped into an xc4vsx55 FPGA. Our results show that an FPGA implementation with fixed-point arithmetic at 87.4MHz can run over 250 times faster than a Core2 Duo processor at 2.2GHz, and more than two times faster than an nVidia Geforce 7900GTX processor with 24 pipelines at 650MHz.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Black, F., Scholes, M.S.: The pricing of options and corporate liabilities. Journal of Political Economics 81, 637–659 (1973)
Celoxica, http://www.celoxica.com
Constantinides, G.A.: Word-length optimization for differentiable nonlinear systems. ACM Trans. on Design Automation of Elect. Sys. 11(1), 26–43 (2006)
Hull, J.C.: Options, Futures and Other Derivatives, 6th edn. Prentice-Hall, Englewood Cliffs (2005)
Morris, G.W., Aubury, M.: Design space exploration of the European option benchmark using hyperstreams. In: Proc. Int. Conf. on Field Programmable Logic and Applications, IEEE, Los Alamitos (2007)
Thomas, D.B., Bower, J.A., Luk, W.: Automatic generation and optimisation of reconfigurable financial Monte-Carlo simulations. In: IEEE Int. Conf. on Application-Specific Systems, Architectures and Processors (2007)
Weaver, N., Markovskiy, Y., Patel, Y., Wawrzynek, J.: Post-placement C-slow retiming for the Xilinx Virtex FPGA. In: Proc. Int. Symp. on FPGAs, pp. 185–194. ACM Press, New York (2003)
Xilinx Inc. Virtex 4 FPGA handbook (2004)
Xilinx Inc. Floating-point operator v3.0 manual (2006)
Wilton, S.W., et al.: The impact of pipelining on energy per operation in Field-Programmable Gate Arrays. In: Becker, J., Platzner, M., Vernalde, S. (eds.) FPL 2004. LNCS, vol. 3203, pp. 719–728. Springer, Heidelberg (2004)
Zhang, G.L., et al.: Reconfigurable acceleration for Monte Carlo based financial simulation. In: Proc. Int. Conf. on Field-Programmable Technology, pp. 215–224. IEEE, Los Alamitos (2005)
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 2008 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Jin, Q., Thomas, D.B., Luk, W., Cope, B. (2008). Exploring Reconfigurable Architectures for Binomial-Tree Pricing Models. In: Woods, R., Compton, K., Bouganis, C., Diniz, P.C. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2008. Lecture Notes in Computer Science, vol 4943. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-78610-8_24
Download citation
DOI: https://doi.org/10.1007/978-3-540-78610-8_24
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-78609-2
Online ISBN: 978-3-540-78610-8
eBook Packages: Computer ScienceComputer Science (R0)