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On Formal Equivalence Verification of Hardware

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Computer Science – Theory and Applications (CSR 2008)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 5010))

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Abstract

When modeling the logic functionality, hardware can be viewed as a Finite State Machine (FSM) [7]. The power-up state of hardware cannot be determined uniquely, therefore the FSM modeling the hardware does not have an initial state (or a set of initial states). Instead, it has a set of legal operation states, and it must be brought into this set of operation states from any power-up state by a reboot sequence.

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References

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Authors and Affiliations

  1. Formal Technology and Logic Group, Intel Corporation, Haifa, Israel

    Zurab Khasidashvili

Authors
  1. Zurab Khasidashvili
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Editor information

Edward A. Hirsch Alexander A. Razborov Alexei Semenov Anatol Slissenko

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© 2008 Springer-Verlag Berlin Heidelberg

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Khasidashvili, Z. (2008). On Formal Equivalence Verification of Hardware . In: Hirsch, E.A., Razborov, A.A., Semenov, A., Slissenko, A. (eds) Computer Science – Theory and Applications. CSR 2008. Lecture Notes in Computer Science, vol 5010. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-79709-8_3

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  • DOI: https://doi.org/10.1007/978-3-540-79709-8_3

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-79708-1

  • Online ISBN: 978-3-540-79709-8

  • eBook Packages: Computer ScienceComputer Science (R0)

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