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Revisiting SIMD Programming

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Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 5234))

Abstract

Massively parallel SIMD array architectures are making their way into embedded processors. In these architectures, a number of identical processing elements having small private storage and using asynchronous I/O for accessing large shared memory executes the same instruction in lockstep.

In this paper, we outline a simple extension to the C language, called Cn, used for programming a commercial SIMD array architecture. The design of Cn is based on the concept of the SIMD array type architecture and revisits first principles of designing efficient and portable parallel programming languages. Cn has a low level of abstraction and can also be seen as an intermediate language in the compilation from higher level parallel languages to machine code.

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References

  1. Parhami, B.: SIMD machines: do they have a significant future? SIGARCH Comput. Archit. News 23(4), 19–22 (1995)

    Article  Google Scholar 

  2. Barnes, G.H., Brown, R.M., Kato, M., Kuck, D.J., Slotnick, D.L., Stokes, R.A.: The Illiac IV computer. IEEE Trans. Computers C-17(8), 746–757 (1968)

    Article  Google Scholar 

  3. ClearSpeed Technology: The CSX architecture, http://www.clearspeed.com/

  4. Snyder, L.: The design and development of ZPL. In: Proc. of the third ACM SIGPLAN conference on History of programming languages (HOPL III), pp. 8–37. ACM Press, New York (2007)

    Google Scholar 

  5. Slotnick, D.: The conception and development of parallel processors—a personal memoir. IEEE Annals of the History of Computing 4(1), 20–30 (1982)

    Article  Google Scholar 

  6. Wilkes, M.V.: The lure of parallelism and its problems. In: Computer Perspectives. Morgan Kaufmann, San Francisco (1995)

    Google Scholar 

  7. Snyder, L.: Type architecture, shared memory and the corollary of modest potential. Annual Review of Computer Science 1, 289–317 (1986)

    Article  Google Scholar 

  8. Kennedy, K., Koelbel, C., Zima, H.: The rise and fall of High Performance Fortran: an historical object lesson. In: Proc. of the third ACM SIGPLAN conference on History of programming languages (HOPL III), pp. 7–22. ACM Press, New York (2007)

    Google Scholar 

  9. American National Standards Institute: ANSI/ISO/IEC 9899-1999: Programming Languages – C (1999)

    Google Scholar 

  10. Lawrie, D.H., Layman, T., Baer, D., Randal, J.M.: Glypnir—a programming language for Illiac IV. Commun. ACM 18(3), 157–164 (1975)

    Article  MATH  Google Scholar 

  11. Stevens Jr., K.: CFD—a Fortran-like language for the Illiac IV. SIGPLAN Not. 10(3), 72–76 (1975)

    Article  Google Scholar 

  12. Perrott, R.H.: A language for array and vector processors. ACM Trans. Program. Lang. Syst. 1(2), 177–195 (1979)

    Article  MATH  Google Scholar 

  13. Li, K.C., Schwetman, H.: Vector C: a vector processing language. Journal of Parallel and Distributed Computing 2(2), 132–169 (1985)

    Article  Google Scholar 

  14. Knobe, K., Lukas, J.D., Steele Jr., G.L.: Data optimization: allocation of arrays to reduce communication on SIMD machines. J. Parallel Distrib. Comput. 8(2), 102–118 (1990)

    Article  Google Scholar 

  15. Weiss, M.: Strip mining on SIMD architectures. In: Proc. of the 5th International Conference on Supercomputing (ICS), pp. 234–243. ACM Press, New York (1991)

    Chapter  Google Scholar 

  16. Rose, J.R., Steele Jr., G.L.: C*: An extended C language for data parallel programming. In: Proc. of the 2nd International Conference on Supercomputing (ICS), vol. 2, pp. 2–16 (1987)

    Google Scholar 

  17. MasPar Computer Corporation: MasPar Programming Language (ANSI C compatible MPL) Reference Manual (1992)

    Google Scholar 

  18. Kyo, S., Okazaki, S., Arai, T.: An integrated memory array processor for embedded image recognition systems. IEEE Trans. Computers 56(5), 622–634 (2007)

    Article  MathSciNet  Google Scholar 

  19. Christy, P.: Software to support massively parallel computing on the MasPar MP-1. In: Proc. of the 35th IEEE Computer Society International Conference (Compcon Spring), pp. 29–33 (1990)

    Google Scholar 

  20. Allen, R., Kennedy, K.: Optimizing Compilers for Modern Architectures. Morgan Kaufmann, San Francisco (2002)

    Google Scholar 

  21. Freescale Semiconductor: AltiVec technology programming interface manual (1999)

    Google Scholar 

  22. Bradley, C., Gaster, B.R.: Exploiting loop-level parallelism for SIMD arrays using OpenMP. In: Proc. of the 3rd International Workshop on OpenMP (IWOPM) (2007)

    Google Scholar 

  23. Tarditi, D., Puri, S., Oglesby, J.: Accelerator: using data parallelism to program GPUs for general-purpose uses. In: Proc. of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-XII), pp. 325–335. ACM Press, New York (2006)

    Chapter  Google Scholar 

  24. Fatahalian, K., Horn, D.R., Knight, T.J., Leem, L., Houston, M., Park, J.Y., Erez, M., Ren, M., Aiken, A., Dally, W.J., Hanrahan, P.: Sequoia: programming the memory hierarchy. In: Proc. of the 2006 ACM/IEEE Conference on Supercomputing (SC), pp. 83–92. ACM Press, New York (2006)

    Chapter  Google Scholar 

  25. ACE Associated Compiler Experts: The CoSy compiler development system, http://www.ace.nl/

  26. Kim, H.: Region-based register allocation for EPIC architectures. PhD thesis, Department of Computer Science, New York University (2001)

    Google Scholar 

  27. Lokhmotov, A., Mycroft, A., Richards, A.: Delayed side-effects ease multi-core programming. In: Kermarrec, A.-M., Bougé, L., Priol, T. (eds.) Euro-Par 2007. LNCS, vol. 4641. Springer, Heidelberg (2007)

    Chapter  Google Scholar 

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Vikram Adve María Jesús Garzarán Paul Petersen

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Lokhmotov, A., Gaster, B.R., Mycroft, A., Hickey, N., Stuttard, D. (2008). Revisiting SIMD Programming. In: Adve, V., Garzarán, M.J., Petersen, P. (eds) Languages and Compilers for Parallel Computing. LCPC 2007. Lecture Notes in Computer Science, vol 5234. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-85261-2_3

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  • DOI: https://doi.org/10.1007/978-3-540-85261-2_3

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-85260-5

  • Online ISBN: 978-3-540-85261-2

  • eBook Packages: Computer ScienceComputer Science (R0)

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