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Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 5226))

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Abstract

A new test data compression scheme is introduced. This scheme encodes the test data provided by the core vendor, using a new and very effective compression scheme based on OLEL coding and neighboring bit-wise exclusive-or transform(OCNBET). Codeword is divided into two parts according to the position: odd bits and even bits. The odd bits of codeword are used to represent the length of runs and the even bits of codeword are used to represent whether a run is finished. Furthermore, a neighboring bit-wise exclusive-or transform is introduced to increase the probability of runs of 0s in the transformed data, so significant compression improvements and power efficient compared with the already known schemes are achieved. A simple architecture is proposed for decoding the compressed data on chip. Its hardware overhead is very low and comparable to that of the most efficient methods in the literature. Experimental results for the six largest ISCAS-89 benchmark circuits show that the proposed scheme is obviously better than the already known schemes in the aspects of compression ratio, power and the decompression structure.

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References

  1. Chandra, C., Chakrabarty, K.: System-On-A-Chip Test-Data Compression and Decompression Architectures Based on Golomb Codes. IEEE CAD/ICAS 20, 355–368 (2001)

    Google Scholar 

  2. Jas, J., Ghosh, D., Touba, N.: An Efficient Test Vector Compression Scheme Using Selective Huffman Coding. IEEE CAD 21, 797–806 (2003)

    Google Scholar 

  3. Gonciari, B., Hashimi, A., Nicolici, G.: Variable-Length Input Huffman Coding for Systemon-a-chip Test. IEEE CAD 22, 783–796 (2003)

    Google Scholar 

  4. Chandra, C., Chakrabarty, K.: Frequency-Directed Run-Length Codes with Application to System-on-a-chip Test Data Compression. In: Proceedings of VTS, pp. 42–47 (2001)

    Google Scholar 

  5. Balakrishnan, B., Touba, N.: Relating Entropy Theory to Test Data Compression. In: Proceedings of ETS, pp. 94–99 (2004)

    Google Scholar 

  6. Reda, C., Orailoglu, J.: Reducing Test Application Time through Test Data Mutation Encoding. In: Proceeding of DATE, pp. 387–393 (2002)

    Google Scholar 

  7. Jas, J., Touba, N.: Using an Embedded Processor for Efficient Deterministic Testing of Systems-on-a-Chip. In: Proceedings of ICCD, pp. 418–423 (1999)

    Google Scholar 

  8. Lin, C., Chen, L.: A Cocktail Approach On Random Access Scan Toward Low Power and High Efficiency Test. In: Proceedings of ICCAD, pp. 94–99 (2005)

    Google Scholar 

  9. Barnhart, D., Distler, O., Farnsworth, A., Ferko, B.: Extending OPMISR beyond 10x Scan Test Efficiency. IEEE Design & Test Compututer, 1965–1973 (2002)

    Google Scholar 

  10. Jas, J., Touba, N.: Test Data Compression Technique for Embedded Cores Using Virtual Scan Chains. IEEE VLSI 12, 775–780 (2004)

    Article  Google Scholar 

  11. Pandey, A., Patel, J.: An Incremental Algorithm For Test Generation in Illinois Scan Architecture Based Designs. In: Proceedings of DATE, pp. 368–375 (2002)

    Google Scholar 

  12. Bayraktaroglu, I., Orailoglu, A.: Test Volume and Application Time Reduction Through Scan Chain Concealment. In: Proceedings of DAC, pp. 151–155 (2001)

    Google Scholar 

  13. Bayraktaroglu, I., Orailoglu, A.: Decompression Hardware Determination for Test Volume and Time Reduction Through Unified Test Pattern Compaction and Compression. In: Proceedings of VTS, pp. 113–120 (2003)

    Google Scholar 

  14. Li, L., Chakrabarty, K.: Deterministic BIST Based on a Reconfigurable Interconnection Network. In: Proceedings of ITC, pp. 460–469 (2003)

    Google Scholar 

  15. Synopsys Inc., http://www.synopsys.com/

  16. Rajski, J.: Embedded Deterministic Test. IEEE TCAD 23, 776–792 (2004)

    Google Scholar 

  17. Tang, H., Reddy, S., Pomeranz, I.: On Reducing Test Data Volume and Test Application Time for Multiple Scan Chain Designs. In: Proceedings of ITC, pp. 1079–1088 (2003)

    Google Scholar 

  18. Brglez, F.: Combinational Profiles of Sequential Benchmark Circuits. In: Proc of 1989 International Symposium on Circuits and Systems, pp. 1929–1934 (1989)

    Google Scholar 

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© 2008 Springer-Verlag Berlin Heidelberg

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Ma, J. (2008). A Test Data Compression Scheme for Reducing Power Based on OLELC and NBET. In: Huang, DS., Wunsch, D.C., Levine, D.S., Jo, KH. (eds) Advanced Intelligent Computing Theories and Applications. With Aspects of Theoretical and Methodological Issues. ICIC 2008. Lecture Notes in Computer Science, vol 5226. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-87442-3_90

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  • DOI: https://doi.org/10.1007/978-3-540-87442-3_90

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-87440-9

  • Online ISBN: 978-3-540-87442-3

  • eBook Packages: Computer ScienceComputer Science (R0)

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