Skip to main content

Encoding Queues in Satisfiability Modulo Theories Based Bounded Model Checking

  • Conference paper

Part of the book series: Lecture Notes in Computer Science ((LNAI,volume 5330))

Abstract

Using a Satisfiability Modulo Theories (SMT) solver as the back-end in SAT-based software model checking allows common data types to be represented directly in the language of the solver. A problem is that many software systems involve first-in-first-out queues but current SMT solvers do not support the theory of queues. This paper studies how to encode queues in the context of SMT-based bounded model checking, using only widely supported theories such as linear arithmetic and uninterpreted functions. Various encodings with considerably different compactness and requirements for available theories are proposed. An experimental comparison of the relative efficiency of the encodings is given.

This work has been financially supported by the Academy of Finland (project 112016), Helsinki Graduate School in Computer Science and Engineering, and Jenny and Antti Wihuri Foundation.

This is a preview of subscription content, log in via an institution.

Buying options

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   84.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Biere, A., Cimatti, A., Clarke, E.M., Zhu, Y.: Symbolic model checking without BDDs. In: Cleaveland, W.R. (ed.) TACAS 1999. LNCS, vol. 1579, pp. 193–207. Springer, Heidelberg (1999)

    Chapter  Google Scholar 

  2. Dubrovin, J., Junttila, T.: Symbolic model checking of hierarchical UML state machines. In: ACSD 2008, pp. 108–117. IEEE Press, Los Alamitos (2008)

    Google Scholar 

  3. Dubrovin, J., Junttila, T., Heljanko, K.: Symbolic step encodings for object based communicating state machines. In: Barthe, G., de Boer, F.S. (eds.) FMOODS 2008. LNCS, vol. 5051, pp. 96–112. Springer, Heidelberg (2008)

    Chapter  Google Scholar 

  4. Cimatti, A., Clarke, E., Giunchiglia, E., Giunchiglia, F., Pistore, M., Roveri, M., Sebastiani, R., Tacchella, A.: NuSMV version 2: An opensource tool for symbolic model checking. In: Brinksma, E., Larsen, K.G. (eds.) CAV 2002. LNCS, vol. 2404, pp. 359–364. Springer, Heidelberg (2002)

    Chapter  Google Scholar 

  5. de Moura, L.M., Dutertre, B., Shankar, N.: A tutorial on satisfiability modulo theories. In: Damm, W., Hermanns, H. (eds.) CAV 2007. LNCS, vol. 4590, pp. 20–36. Springer, Heidelberg (2007)

    Chapter  Google Scholar 

  6. Nieuwenhuis, R., Oliveras, A., Tinelli, C.: Solving SAT and SAT modulo theories: From an abstract Davis–Putnam–Logemann–Loveland procedure to DPLL(T). Journal of the ACM 53(6), 937–977 (2006)

    Article  MathSciNet  MATH  Google Scholar 

  7. Bozzano, M., Bruttomesso, R., Cimatti, A., Junttila, T.A., van Rossum, P., Schulz, S., Sebastiani, R.: MathSAT: Tight integration of SAT and mathematical decision procedures. Journal of Automated Reasoning 35(1–3), 265–293 (2005)

    Article  MathSciNet  MATH  Google Scholar 

  8. Bjørner, N.S.: Integrating Decision procedures for Temporal Verification. PhD thesis, Stanford University (1998)

    Google Scholar 

  9. OMG: UML 2.0 superstructure specification (2005), http://www.omg.org

  10. International Telecommunication Union Geneva, Switzerland: Recommendation Z.100 (03/93) - CCITT specification and description language (SDL) (1993)

    Google Scholar 

  11. Biere, A., Heljanko, K., Junttila, T.A., Latvala, T., Schuppan, V.: Linear encodings of bounded LTL model checking. Logical Methods in Computer Science 2(5) (2006)

    Google Scholar 

  12. Sheeran, M., Singh, S., Stålmarck, G.: Checking safety properties using induction and a SAT-solver. In: Johnson, S.D., Hunt Jr., W.A. (eds.) FMCAD 2000. LNCS, vol. 1954, pp. 108–125. Springer, Heidelberg (2000)

    Chapter  Google Scholar 

  13. Eén, N., Sörensson, N.: Temporal induction by incremental SAT solving. In: BMC 2003. Electronic Notes in Theoretical Computer Science, vol. 89, pp. 541–638. Elsevier, Amsterdam (2003)

    Google Scholar 

  14. Oppen, D.C.: Reasoning about recursively defined data structures. Journal of the ACM 27(3), 403–411 (1980)

    Article  MathSciNet  MATH  Google Scholar 

  15. Lahiri, S.K., Seshia, S.A., Bryant, R.E.: Modeling and verification of out-of-order microprocessors in UCLID. In: Aagaard, M.D., O’Leary, J.W. (eds.) FMCAD 2002. LNCS, vol. 2517, pp. 142–159. Springer, Heidelberg (2002)

    Chapter  Google Scholar 

  16. Dutertre, B.: System description: Yices 1.0.10. SMT-COMP 2007 tool description paper (2007), http://www.smtcomp.org/2007/participants.shtml

  17. Ganai, M.K., Gupta, A., Ashar, P.: Efficient modeling of embedded memories in bounded model checking. In: Alur, R., Peled, D.A. (eds.) CAV 2004. LNCS, vol. 3114, pp. 440–452. Springer, Heidelberg (2004)

    Chapter  Google Scholar 

  18. Ganai, M.K., Gupta, A., Ashar, P.: Verification of embedded memory systems using efficient memory modeling. In: DATE 2005, pp. 1096–1101. IEEE Computer Society, Los Alamitos (2005)

    Google Scholar 

  19. Clarke, E.M., Grumberg, O., Peled, D.A.: Model Checking. The MIT Press, Cambridge (1999)

    Google Scholar 

  20. Stump, A., Barrett, C.W., Dill, D.L., Levitt, J.R.: A decision procedure for an extensional theory of arrays. In: LICS 2001, pp. 29–37. IEEE Computer Society, Los Alamitos (2001)

    Google Scholar 

  21. Nieuwenhuis, R., Oliveras, A.: Fast congruence closure and extensions. Information and Computation 205, 557–580 (2007)

    Article  MathSciNet  MATH  Google Scholar 

  22. de Moura, L.M., Bjørner, N.: Z3: An efficient SMT solver. In: Ramakrishnan, C.R., Rehof, J. (eds.) TACAS 2008. LNCS, vol. 4963, pp. 337–340. Springer, Heidelberg (2008)

    Chapter  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2008 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Junttila, T., Dubrovin, J. (2008). Encoding Queues in Satisfiability Modulo Theories Based Bounded Model Checking. In: Cervesato, I., Veith, H., Voronkov, A. (eds) Logic for Programming, Artificial Intelligence, and Reasoning. LPAR 2008. Lecture Notes in Computer Science(), vol 5330. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-89439-1_21

Download citation

  • DOI: https://doi.org/10.1007/978-3-540-89439-1_21

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-89438-4

  • Online ISBN: 978-3-540-89439-1

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics