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Pacific-Rim Conference on Multimedia

PCM 2008: Advances in Multimedia Information Processing - PCM 2008 pp 834–837Cite as

High Performance Hardware Architecture of Linear Filters for Intelligent Video Processing

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Part of the book series: Lecture Notes in Computer Science ((LNISA,volume 5353))

Abstract

Image filtering is an essential process in the field of image processing, and linear image filters with large kernels are especially significant for computer vision or intelligent video processing. In this paper, a high performance hardware architecture of linear image filters, which is designed for embedded system in mobile devices, is proposed and analyzed. This linear filter hardware is capable of dealing with a 15 by 15 kernel by using massively parallel processing elements, and it offers a set of configurable parameters, which generalizes the functionality to handle different kinds of linear filters in most applications.

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References

  1. Kim, D.H., Kim, Y.S., Park, H.S.: Fast and efficient face image browsing system on consumer electronics devices. In: Proceedings of IEEE International Symposium on Multimedia Workshops, pp. 329–334 (December 2007)

    Google Scholar 

  2. Kyo, S., Okazaki, S., Arai, T.: An integrated memory array processor for embedded image recognition systems. IEEE Transactions on Computers 56(5), 622–634 (2007)

    Article  MathSciNet  Google Scholar 

  3. Abbo, A., Kleihorst, R., Choudhary, V., Sevat, L., Wielage, P., Mouy, S., Vermeulen, B., Heijligers, M.: Xetal-II: A 107 GOPS, 600mW massively parallel processor for video scene analysis. IEEE Journal of Solid-State Circuits 43(1), 192–201 (2008)

    Article  Google Scholar 

  4. Grigorescu, S.E., Petkov, N., Kruizinga, P.: Comparison of texture features based on Gabor filters. IEEE Transactions on Image Processing 11(10), 1160–1167 (2002)

    Article  MathSciNet  Google Scholar 

  5. Chen, T.-W., Sun, C.-H., Bai, J.-Y., Chen, H.-R., Chien, S.-Y.: Architectural analyses of K-Means silicon intellectual property for image segmentation. In: Proceedings of IEEE International Symposium on Circuits and Systems, pp. 2578–2581 (May 2008)

    Google Scholar 

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Author information

Authors and Affiliations

  1. Media IC and System Lab Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, BL-421, No. 1, Sec. 4, Roosevelt Rd., Taipei, 106, Taiwan

    Tse-Wei Chen & Shao-Yi Chien

Authors
  1. Tse-Wei Chen
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  2. Shao-Yi Chien
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Editor information

Editors and Affiliations

  1. Department of Engineering Science, National Cheng Kung University, No.1, University Road, 701, Tainan City, Taiwan

    Yueh-Min Ray Huang

  2. National Laboratory of Pattern Recognition, Institute of Automation, Chinese Academy of Sciences, 95, Zhongguancun East Road, 100190, Beijing, China

    Changsheng Xu

  3. Institute of Biomedical Engineering, National Cheng Kung University, No. 1, University Road, 701, Tainan City, Taiwan

    Kuo-Sheng Cheng

  4. Department of Electrical Engineering, National Cheng Kung University, No. 1, University Road, 701, Tainan City, Taiwan

    Jar-Ferr Kevin Yang

  5. Department of Electrical and Computer Engineering, Concordia University, S-EV005.139, 1515 St. Catherine West, Montreal, H4G 2W1, Quebec, Canada

    M. N. S. Swamy

  6. Microsoft Research Asia, 5/F, Beijing Sigma Center, No. 49, Zhichun Road, Hai Dian District, 100080, Beijing, China

    Shipeng Li

  7. Department of Information Management, National Kaohsiung University of Applied Sciences, No. 415, Jiangong Road, Sanmin District, 80778, Kaohsiung, Taiwan

    Jen-Wen Ding

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© 2008 Springer-Verlag Berlin Heidelberg

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Cite this paper

Chen, TW., Chien, SY. (2008). High Performance Hardware Architecture of Linear Filters for Intelligent Video Processing. In: Huang, YM.R., et al. Advances in Multimedia Information Processing - PCM 2008. PCM 2008. Lecture Notes in Computer Science, vol 5353. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-89796-5_93

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  • DOI: https://doi.org/10.1007/978-3-540-89796-5_93

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-89795-8

  • Online ISBN: 978-3-540-89796-5

  • eBook Packages: Computer ScienceComputer Science (R0)

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