Abstract
As the number of cores in CMPs increases, NoC is projected to be the dominant communication fabric. Increase in the number of cores brings an important issue to the forefront, the issue of chip power consumption, which is projected to increase rapidly with the increase in number of cores. Since NoC infrastructure contributes significantly to the total chip power consumption, reducing NoC power is crucial. While circuit level techniques are important in reducing NoC power, architectural and software level approaches can be very effective in optimizing power consumption. Any such technique power saving technique should be scalable and have minimal adverse impact on performance. We propose a dynamic, communication link usage based, proactive link power management scheme. This scheme,using a Markov model, proactively manages communication link turn-ons and turn-offs, which results in negligible performance degradation and significant power savings. We show that our prediction scheme is about 98% accurate for the SPEC OMP benchmarks and about 93% over all applications experimented. This accuracy helps us achieve link power savings of up to 44% and an average link power savings of 23.5%. More importantly, it incurs performance penalties as low as 0.3% on average.
This research is supported in part by NSF grants 0811687, 0720645, 0720749, 0702519, 0444345 and a grant from GSRC.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
Cell broadband engine - white paper. IBM (2006)
Benini, L., Micheli, G.D.: Powering networks on chips: Energy-efficient and reliable interconnect design for socs. In: Proc. ISSS (2001)
Chen, X., Peh, L.-S.: Leakage power modeling and optimization in interconnection networks. In: Proc. ISLPED (2003)
Dally, W.J., Towles, B.: Principles and Practices of Interconnection Networks. Morgan Kaufmann, San Francisco (2004)
Dhodapkar, A.S., Smith, J.E.: Managing multi-configurable hardware via dynamic working set analysis. In: Proc. ISCA (2002)
Dhodapkar, A.S., Smith, J.E.: Comparing program phase detection techniques. In: Proc. MICRO (2003)
Duato, J., et al.: Interconnection Networks: An Engineering Approach. IEEE CS Press, Los Alamitos (1997)
Flautner, K., et al.: Drowsy caches: Simple techniques for reducing leakage power. In: Proc. ISCA (2002)
Galles, M.: Spider: A high-speed network interconnect. IEEE Micro. 17(1), 34–39 (1997)
Hetherington, R.: The UltraSparc T1 processor. SUN (2005)
Huang, M.C., et al.: Positional adaptation of processors: Application to energy reduction. In: Proc. ISCA (2003)
Isci, C., et al.: An analysis of efficient multi-core global power managment policies: Maximizing peformance for a given power budget. In: Proc. MICRO (2006)
Isci, C., Martonosi, M.: Phase characterization for power: Evaluating control flow based and event counter based techniques. In: Proc. HPCA (2006)
Joseph, D., Grunwald, D.: Prefetching using markov predictors. In: Proc. ISCA (1997)
Kim, C., et al.: Nonuniform cache architecture for wire-delay dominated network-on-chip caches. In: IEEE Micro.: Micro’s Top Picks from Computer Architecture Conferences (2003)
Latouche, G., Ramaswami, V.: Introduction to matrix analytic methods in stochastic modeling. In: ASA SIAM, PH Distributions (1999)
Lau, J., et al.: Transition phase classification and prediction. In: Proc. HPCA (2005)
Li, F., et al.: Compiler-directed proactive power management for networks. In: Proc. CASES (2005)
Li, F., et al.: Profile-driven energy reduction in network-on-chips. In: Proc. PLDI (2007)
Li, J., Martinez, J.F.: Dynamic power-performance adaptation of parallel computation on chip multiprocessors. In: Proc. HPCA (2006)
Magnusson, P.S., et al.: Simics: A full system simulation platform. Computer 35(2), 50–58 (2002)
Oly, J., Reed, D.A.: Markov model prediction of i/o requests for scientific applications. In: Proc. ICS (2002)
Perelman, E., et al.: Detecting phases in parallel applications on shared memory architectures. In: IPDPS (2006)
Ramanathan, R.: Intel multi-core processors: Making the move to quad-core and beyond. Intel White paper, Intel Corporation (2006)
Shang, L., et al.: Dynamic voltage scaling with links for power optimization of interconnection networks. In: Proc. HPCA (2003)
Sharkey, J., et al.: Evaluating design tradeoffs in on-chip power management for cmps. In: Proc. ISLPED (2007)
Sherwood, T., et al.: Discovering and exploiting program phases. In: IEEE Micro: Micro’s Top Picks from Computer Architecture Conferences (December 2003)
Shin, D., Kim, J.: Power-aware communication optimization for network-on-chips with voltage scalable links. In: Proc. CODES+ISSS (2004)
Simunic, T., Boyd, S.: Managing power consumption in networks on chips. In: Proc. DATE (2002)
Singh, J.P., Weber, W.-D., Gupta, A.: Splash: Stanford parallel applications for shared-memory. Computer Architecture News 20(1), 5–44
Soteriou, V., Peh, L.-S.: Dynamic power management for power optimization of interconnecttion networks using on/off links. In: Proc. HOT-I (2003)
Soteriou, V., Peh, L.-S.: Design space exploration of power-aware on/off interconnection networks. In: Proc. ICCD (2004)
Timothy, G.H., Mattson, G.: An overview of the Intel TFLOPS Supercomputer. Intel. Technology Journal (1998)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2009 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Muralidhara, S.P., Kandemir, M. (2009). Communication Based Proactive Link Power Management. In: Seznec, A., Emer, J., O’Boyle, M., Martonosi, M., Ungerer, T. (eds) High Performance Embedded Architectures and Compilers. HiPEAC 2009. Lecture Notes in Computer Science, vol 5409. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-92990-1_16
Download citation
DOI: https://doi.org/10.1007/978-3-540-92990-1_16
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-92989-5
Online ISBN: 978-3-540-92990-1
eBook Packages: Computer ScienceComputer Science (R0)