Abstract
Process variations, which lead to timing and power variations across identically-designed components, have been identified as one of the key future design challenges by the semiconductor industry. Using worst case latency/power assumptions is one option to address process variations. This option, while simplifying the problem, is becoming less and less attractive as its performance and power costs keep increasing. As a result, exploring options that allow the software to have knowledge about the actual latency/power consumption values is critical for future systems. Targeting systematic process variations, this paper makes two contributions. First, we discuss how we can assign threads to the cores of a chip multiprocessor (CMP) with process variations in mind and show the energy-delay product (EDP) benefits such a process variation-aware thread mapping can bring. Second, we study the benefits of varying the frequencies on a subset of the cores to increase EDP savings. We propose and evaluate integer linear programming based thread mapping schemes in both studies. While these schemes operate with profile data, they can be made to work with partial profiling as well with the help of curve fitting. We tested our schemes using both sequential and multi-threaded benchmarks from different suites and the results collected indicate that we can achieve EDP savings as much as 73.4%, with an average saving of 37.1% over a process variation agnostic scheme.
This research is supported in part by NSF grants 0811687, 0720645, 0720749, 0702519, 0444345 and a grant from GSRC.
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References
Applications of optimization with Xpress-MP, http://www.dashoptimization.com/
Intel 45nm hi-k silicon technology, http://www.intel.com/technology/architecture-silicon/45nm-core2/
International technology roadmap for semiconductors (2005), http://public.itrs.net/
NAS NPB benchmarks 3.2, http://www.nas.nasa.gov/Software/NPB/
Virtutech Simics 3.0, http://www.virtutech.com/
Balakrishnan, S., Rajwar, R., Upton, M., Lai, K.: The impact of performance asymmetry in emerging multicore architectures. In: Proceedings of International Symposium of Computer Architecture (2005)
Banerjee, N., Karakonstantis, G., Roy, K.: Process variation tolerant low power DCT architecture. In: Proceedings of Design, Automation and Test in Europe (2007)
Becchi, M., Crowley, P.: Dynamic thread assignment on heterogeneous multiprocessor architectures. In: Proceedings of Computing Frontiers (2006)
Borkar, S.: VLSI Design Challenges for Gigascale Integration. In: Proceedings of International Conference on VLSI Design (2005)
Borkar, S.: Designing reliable systems from unreliable components: The challenges of transistor variability and degradation. IEEE Micro. 25(6) (2005)
Bronevetsky, G., Marques, D., Pingali, K., Szwed, P., Schulz, M.: Application-level checkpointing for shared memory programs. In: Proceedings of Architecture Support for Programming Languages and Operating Systems (2004)
Brooks, D., Tiwari, V., Martonosi, M.: Wattch: a framework for architectural-level power analysis and optimizations. In: Proceedings of International Symposium of Computer Architecture (2000)
Cain, J.P., Zhang, H., Spanos, C.J.: Optimum sampling for characterization of systematic variation in photolithography. In: Proceedings of SPIE, vol. 4689 (2002)
Choi, M.: Modeling of deterministic within-die variation in timing analysis, leakage current analysis, and delay fault diagnosis. School of Electrical and Computer Engineering Theses and Dissertations, Georgia Institute of Technology (2007)
Donald, J., Martonosi, M.: Power efficiency for variation-tolerant multicore processors. In: Proceedings of International Symposium of Computer Architecture (2006)
Fetzer, E.S.: Using adaptive circuits to mitigate process variations in a microprocessor design. IEEE Design & Test 23(6) (2006)
Gonzalez, R., Horowitz, M.: Energy dissipation in general purpose microprocessors. In: Proceedings of Internationl Symposium on Low Power Electronics (1995)
Humenay, E., Tarjan, D., Skadron, K.: Impact of process variations on multicore performance symmetry. In: Proceedings of Design, Automation and Test in Europe (April 2007)
Ipek, E., Kirman, M., Kirman, N., Martinez, J.F.: Core fusion: accommodating software diversity in chip multiprocessors. In: Proceedings of International Symposium of Computer Architecture (2007)
Jin, H., Frumkin, M., Yan, J.: The OpenMP implementation of NAS parallel benchmarks and its performance. Technical Report NAS-99-011 (1999)
Kahng, A.B., Park, C.-H., Sharma, P., Wang, Q.: Lens aberration aware timing-driven placement. In: Proceedings of Design, Automation and Test in Europe (2006)
Kang, K., Kim, K., Roy, K.: Variation resilient low-power circuit design methodology using on-chip phase locked loop. In: Proceedings of Design Automation Conference (2007)
Kim, C., Sethumadhavan, S., Govindan, M., Ranganathan, N., Gulati, D., Burger, D., Keckler, S.W.: Composable lightweight processors. In: Proceedings of International Symposium on Microarchitecture (2007)
Kumar, R., Tullsen, D.M., Jouppi, N.P.: Core architecture optimization for heterogeneous chip multiprocessors. In: Proceedings of Parallel Architecture and Compilation Techniques (2006)
Kumar, R., Tullsen, D.M., Ranganathan, P., Jouppi, N.P., Farkas, K.I.: Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance. In: Proceedings of International Symposium of Computer Architecture (2004)
Liang, X., Brooks, D.: Mitigating the impact of process variations on processor register files and execution units. In: Proceedings of International Symposium on Microarchitecture (2006)
Meng, K., Joseph, R.: Process variation aware cache leakage management. In: Proceedings of International Symposium on Low Power Electronics and Design (2006)
Milojičić, D.S., Douglis, F., Paindaveine, Y., Wheeler, R., Zhou, S.: Process migration. ACM Computer Surveys 32(3) (2000)
Roberts, D., Dreslinski, R., Karl, E., Mudge, T., Sylvester, D., Blaauw, D.: When homogeneous becomes heterogeneous: Wearout aware task scheduling for streaming applications. In: Workshop on Operationg System Support for Heterogeneous Multicore Architectures (2007)
Shafi, H., Speight, E., Bennett, J.K.: Raptor: integrating checkpoints and thread migration for cluster management. In: Proceedings of International Symposium on Reliable Distributed Systems (2003)
Teodorescu, R., Torrellas, J.: Variation-aware application scheduling and power management for chip multiprocessors. In: Proceedings of International Symposium of Computer Architecture (2008)
Thoziyoor, S., Muralimanohar, N., Jouppi, N.P.: CACTI 5.0. Hewlett-Packard technical report HPL-2007-167 (2007), http://quid.hpl.hp.com:9082/cacti/
Unsal, O.S., Tschanz, J.W., Bowman, K., De, V., Vera, X., Gonzalez, A., Ergin, O.: Impact of parameter variations on circuits and microarchitecture. IEEE Micro. 26(6) (2006)
Veldema, R., Philippsen, M.: Near overhead-free heterogeneous thread-migration. In: Proceedings of International Conference on Cluster Computing (2005)
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Ding, Y., Kandemir, M., Irwin, M.J., Raghavan, P. (2009). Adapting Application Mapping to Systematic Within-Die Process Variations on Chip Multiprocessors. In: Seznec, A., Emer, J., O’Boyle, M., Martonosi, M., Ungerer, T. (eds) High Performance Embedded Architectures and Compilers. HiPEAC 2009. Lecture Notes in Computer Science, vol 5409. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-92990-1_18
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