Abstract
Aiming for a systematic evaluation of DRAM sense amplifier (SA) performance, the SA is modeled using small signal equivalent circuit approach in order to analyze mismatch effects and to support design robustness concerning technology variations. The statistical mismatch of the SA is replaced by equivalent voltage sources. The switching delay between n- and p-sensing transistors of the SA is also analyzed. This approach supports yield consideration of DRAM sense amplifiers in future technologies.
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Li, Y., Schneider, H., Schnabel, F., Thewes, R., Schmitt-Landsiedel, D. (2009). Latched CMOS DRAM Sense Amplifier Yield Analysis and Optimization. In: Svensson, L., Monteiro, J. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2008. Lecture Notes in Computer Science, vol 5349. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-95948-9_13
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DOI: https://doi.org/10.1007/978-3-540-95948-9_13
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-95947-2
Online ISBN: 978-3-540-95948-9
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