Abstract
Statistical static timing analysis (SSTA) has emerged as a viable technique to capture increasing process variations in 90nm technologies and beyond. To obtain realistic results from a statistical timer, careful attention to the statistical gate delays and correlations between them is required. However when using SSTA early in the design phase, no correlation information is available. This paper addresses this problem and proposes a novel path-based algorithm, which covers arbitrary correlations by computing bounds for the true path delay distribution. Our bounding method is based on the theory of copulas as well as an efficient bounding improvement technique. The efficiency and accuracy of the proposed algorithm is demonstrated on ISCAS’85 benchmark circuits. Over all testcases and all spatial correlation structures the average error of the 95th quantile points is smaller than 7% and the run-time is drastically reduced compared to a transistor level SPICE Monte Carlo simulation.
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Schneider, W., Schmidt, M., Li, B., Schlichtmann, U. (2009). A New Bounding Technique for Handling Arbitrary Correlations in Path-Based SSTA. In: Svensson, L., Monteiro, J. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2008. Lecture Notes in Computer Science, vol 5349. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-95948-9_17
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DOI: https://doi.org/10.1007/978-3-540-95948-9_17
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-95947-2
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