Abstract
The exploitation of reconfigurable architectures is currently increasing for high-performance applications e.g. signal processing systems. Until now however, general purpose processors are typically applied for lowpower applications partly due to the un-optimized design process of FPGA systems. Currently, the increasing requirements even on low-power applications force the investigation of alternative architectures such as FPGAs to enable higher flexibility for such applications. This paper presents a multi-level overview of power optimization for FPGA-based systems. Several novel design considerations for power reduction are described and discussed as well as the achieved results. The main objective of the presented work is to enable the flexibility of reconfigurable architectures even for low-power applications.
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Noguera, J., Esser, R., Paulsson, K., Hübner, M., Becker, J. (2009). Towards Novel Approaches in Design Automation for FPGA Power Optimization. In: Svensson, L., Monteiro, J. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2008. Lecture Notes in Computer Science, vol 5349. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-95948-9_42
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DOI: https://doi.org/10.1007/978-3-540-95948-9_42
Publisher Name: Springer, Berlin, Heidelberg
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