Abstract
Coarse-grained reconfigurable array processors (CGRAs) offer a promising path to high performance and power efficient processing. Increasing power dissipation at interconnect wires that comes with advanced process technologies may become a major problem for heavily interconnected CGRA processors. In our study we show that for a typical 90 nm process technology power in wire interconnects is still a fractional part of total power.
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Berekovic, M., Bouwens, F., Vander Aa, T., Verkest, D. (2009). Interconnect Power Analysis for a Coarse-Grained Reconfigurable Array Processor. In: Svensson, L., Monteiro, J. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2008. Lecture Notes in Computer Science, vol 5349. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-95948-9_45
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DOI: https://doi.org/10.1007/978-3-540-95948-9_45
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-95947-2
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