Abstract
Two main components in AES-GCM (Advanced Encryption Standard with Galois Counter Mode) are an AES engine and a finite field multiplier over GF(2128) in the universal hashing function (GHASH). Because of the inherent computation feedback, the system performance is usually determined by the finite field multiplier based on the known FPGA implementations to date. In this paper, we present the throughput optimization of AES-GCM with a 4-stage pipelined finite field multiplier based on Karatsuba-Ofman algorithm on FPGAs. The critical delay of the pipelined multiplier then matches that of the AES implementation with either the BlockRAM SubBytes, pipelined composite field SubBytes or LUT-based SubBytes. The AES-GCM throughput reaches more than 30Gbps on a single Xilinx Virtex Chip. The experimental results show that we achieve the most efficient AES-GCM implementations on FPGAs to date.
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Zhou, G., Michalik, H., Hinsenkamp, L. (2009). Improving Throughput of AES-GCM with Pipelined Karatsuba Multipliers on FPGAs. In: Becker, J., Woods, R., Athanas, P., Morgan, F. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2009. Lecture Notes in Computer Science, vol 5453. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-00641-8_20
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DOI: https://doi.org/10.1007/978-3-642-00641-8_20
Publisher Name: Springer, Berlin, Heidelberg
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