Abstract
The growth of the reconfigurable systems community exposes diverse requirements with regard to functionality of Electronic Design Automation (EDA) tools. Those targeting reconfigurable design analysis and manipulation require low-level design tools for bitstream debugging and IP core design assurance. While tools for low-level analy sis of design netlists do exist there is a need for a low-level, open-source, extended tool support.
This paper reports a Field Programmable Gate Array (FPGA) Analysis Tool (FAT) being a versatile, modular and open-source tools framework for low-level analysis and verification of FPGA designs. The analysis performed by FAT is based on available Xilinx FPGA device specification data. FAT provides a set of standalone, high-level Application Programming Interfaces (APIs) abstracting the Xilinx FPGA fabric, the placed and routed design netlist and the related bitstream. The operation of FAT is governed by “recipe” scripts. A lightweight graphic front-end allows visualisation of the design within the FPGA fabric. The paper illustrates the application of FAT for bit-pattern analysis of the Virtex-II Pro inter-tile routing and verification of the spatial isolation between designs.
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References
Lotze, J., Fahmy, S., Noguera, J., Doyle, L., Esser, R.: An FPGA-based Cognitive Radio Framework. In: IET Irish Signals and Systems Conference, NUI, Galway, pp. 138–143 (2008)
Bondhugula, U., Devulapalli, A., Fernando, J., Wyckoff, P., Sadayappan, P.: Parallel FPGA-based all-pairs shortest-paths in a directed graph. In: Proceedings of the 20th IEEE International Parallel and Distributed Processing Symposium (IPDPS). IEEE Computer Society, Washington (2006)
McLean, M., Moore, J.: FPGA-based single chip cryptographic solution. Military Embedded Systems, http://www.mil-embedded.com/pdfs/NSA.Mar07.pdf
Huffmire, T., Brotherton, B., Wang, G., Sherwood, T., Kastner, R., Levin, T., Nguyen, T., Irvine, C.: Moats and drawbridges: An isolation primitive for reconfigurable hardware based systems. In: IEEE Symposium on Security and Privacy, pp. 281–295. IEEE Computer Society, Los Alamitos (2007)
Kepa, K., Morgan, F., Kosciuszkiewicz, K., Surmacz, T.: SeReCon: a Secure Dynamic Partial Reconfiguration Controller for SoPCs. In: IEEE Computer Society Annual Symposium on VLSI, pp. 292–297. IEEE Computer Society, Los Alamitos (2008)
Drimer, S., Guneysu, T., Kuhn, M., Paar, C.: Protecting multiple cores in a single FPGA design, http://www.cl.cam.ac.uk/~sd410/papers/protect_many_cores.pdf
Ehliar, A., Liu, D.: Thinking Outside The Flow: Creating Customized Backend Tools For Xilinx Based Designs. In: FPGA World 2007, Sweden (2007)
Steiner, N., Athanas, P.: An Alternate Wire Database for Xilinx FPGAs. In: FCCM 2004: Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 336–337. IEEE Computer Society, Washington (2004)
Thompson, K.: Reflections on trusting trust. In: Communications of the ACM, pp. 761–763. ACM, New York (1984)
Xilinx ISE Foundation, http://www.xilinx.com/ise/logic_design_prod/foundation.htm
JBits 3.0 SDK, http://www.xilinx.com/labs/projects/jbits
Note, J., Rannaud, E.: From the bitstream to the netlist. In: Proceedings of the 16th international ACM/SIGDA symposium on FPGA, pp. 264–264. ACM, New York (2008)
Xilinx Single Chip Crypto Solution, http://www.xilinx.com/esp/aero_def/crypto.htm
Xilinx: Virtex-II Pro User Guide UG012 (v4.0). Xilinx (2005)
Xilinx: Xilinx design language, <XILINX_INST_DIR>/help/data/xdl/xdl.html in ISE 6.1
Raaijmakers, S., Wong, S.: Run-Time Partial Reconfiguration for Removal, Placement and Routing on the Virtex-II Pro. In: Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL 2007). IEEE Computer Society, Amsterdam (2007)
Huebner, M., Braun, L., Becker, J., Claus, C., Stechele, W.: Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs. In: IEEE Computer Society Annual Symposium on VLSI, pp. 41–46. IEEE Computer Society, Los Alamitos (2007)
Krasteva, Y., de la Torre, E., Riesgo, T., Joly, D.: Virtex II FPGA Bitstream Manipulation: Application to Reconfiguration Control Systems. In: Proc. of International Conference on Field Programmable Logic and Applications (FPL 2006). IEEE Computer Society, Los Alamitos (2006)
Steiner, N.: A Standalone Wire Database for Routing and Tracing in Xilinx Virtex, Virtex-E, and Virtex-II FPGAs. Masters thesis (2002)
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Kępa, K., Morgan, F., Kościuszkiewicz, K., Braun, L., Hübner, M., Becker, J. (2009). FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing. In: Becker, J., Woods, R., Athanas, P., Morgan, F. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2009. Lecture Notes in Computer Science, vol 5453. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-00641-8_9
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DOI: https://doi.org/10.1007/978-3-642-00641-8_9
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