Abstract
In this paper, we propose a novel approach to reduce dynamic power in set-associative caches that leverages on a leakage-saving proposal, namely Cache Decay. We thus open the possibility to unify dynamic and leakage management in the same framework. The main intuition is that in a decaying cache, dead lines in a set need not be searched. Thus, rather than trying to predict which cache way holds a specific line, we predict, for each way, whether the line could be live in it. We access all the ways that possibly contain the live line and we call this way selection. In contrast to way-prediction, way-selection cannot be wrong: the line is either in the selected ways or not in the cache. The important implication is that we have a fixed hit time — indispensable for both performance and ease-of-implementation reasons. One would expect way-selection to be inferior to sophisticated way-prediction in terms of the total ways accessed, but in fact it can even do better. To achieve this level of accuracy we use Decaying Bloom filters to track only the live lines in ways — dead lines are automatically purged. We offer efficient implementations of such autonomously Decaying Bloom filters, using novel quasi-static cells. Our prediction approach affords us high-accuracy in narrowing the choice of ways for hits as well as the ability to predict misses — a known weakness of way-prediction — thus outperforming sophisticated way-prediction. Furthermore, our approach scales significantly better than way-prediction to higher associativity. We show that decay is a necessary component in this approach — way-selection and Bloom filters alone cannot compete with sophisticated way-prediction. We compare our approach to Multi-MRU and we show that without even considering leakage savings — we surpass it terms of relative power savings and in relative energy-delay in 4-way (9%) and more so in 8-way (20%) and 16-way caches (31%).
Keywords
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
Baer, J.-L., Wang, W.: On the inclusion properties for multi-level cache hierarchies. In: Proc. of the Int. Symp. of Computer Architecture (1988)
Batson, B., Vijaykumar, T.N.: Reactive-associative caches. In: Proc. of PACT (2001)
Bloom, B.: Space/time trade-offs in hash coding with allowable errors. Commun. ACM 13(7) (1970)
Abella, J., et al.: Iatac: a smart predictor to turn-off l2 cache lines. In: ACM TACO (2005)
Calder, B., et al.: Predictive sequential associative cache. In: Proc. of the Symp. on High-Performance Computer Architecture (1996)
Zhang, C., et al.: Two fast and high-associativity cache schemes. IEEE Micro. 17(5) (1997)
Brooks, D., et al.: Wattch: a framework for architectural-level power analysis and optimizations. In: Proc. of the Int. Symp. of Computer Architecture (2000)
Dharmapurikar, S., et al.: Longest prefix matching using bloom filters (2003)
Zhou, H., et al.: Adaptive mode control: A static-power-efficient cache design. Trans. on Embedded Computing Sys. 2(3) (2003)
Peir, J.-K., et al.: Bloom filtering cache misses for accurate data speculation and prefetching. In: Proc. of the Int. Conference on Supercomputing (2002)
Flautner, K., et al.: Drowsy caches: Simple techniques for reducing leakage power. In: Proc. of the Int. Symp. of Computer Architecture (2002)
Inoue, K., et al.: Way-predicting set-associative cache for high performance and low energy consumption. In: Proc. of ISLPED (1999)
Powell, M., et al.: Reducing set-associative cache energy via way-prediction and selective direct-mapping. In: Proc. of the Int. Symp. on Microarchitecture (2001)
Zhang, M., et al.: Fine-grain cam-tag cache resizing using miss tags. In: Proc. of ISLPED (2002)
Moshovos, A., et al.: Jetty: Snoop filtering for reduced energy consumption in smp servers (2001)
Powell, M., et al.: Gated-vdd: A circuit technique to reduce leakage in deep-submicron cache memories. In: Proc. of ISLPED (2000)
Min, R., et al.: Location cache: a low-power l2 cache system. In: Proc. of ISLPED (2004)
Kaxiras, S., et al.: Cache decay: Exploiting generational behavior to reduce cache leakage power. In: Proc. of the Int. Symp. of Computer Architecture (2001)
Kaxiras, S., et al.: 4t-decay sensors: a new class of small, fast, robust, and low-power, temperature/leakage sensors. In: Proc. of ISLPED (2004)
Kaxiras, S., et al.: A simple mechanism to adapt leakage-control policies to temperature. In: Proc. of ISLPED (2005)
Sethumadhavan, S., et al.: Scalable hardware memory disambiguation for high-ilp processors. In: Proc. of Micro., vol. 24(6) (2004)
Velusamy, S., et al.: Adaptive cache decay using formal feedback control. In: Proc. of the Workshop on Memory Performance Issues (2002)
Yang, S., et al.: An integrated circuit/architecture approach to reducing leakage in deep-submicron high-performance i-caches. In: Proc. of the Int. Symp. on High-Performance Computer Architecture (2001)
Degalahal, V., et al.: Analyzing soft errors in leakage optimized sram design. In: Proc. of the Int. Conference on VLSI Design (2003)
Li, Y., et al.: State-preserving vs. non-state-preserving leakage control in caches. In: Proc. of the Conference on Design, Automation and Test in Europe (2004)
Chishti, Z., et al.: Wire delay is not a problem for smt (in the near future). In: Proc. of the Int. Symp. of Computer Architecture (2004)
Hu, Z., et al.: Managing leakage for transient data: Decay and quasi-static 4t memory cells. In: Proc. of ISLPED (2002)
Borkar, S.: Design challenges of technology scaling. In: Proc. of Micro. (1999)
Wilton, S., Jouppi, N.: Cacti: An enhanced cache access and cycle time model. IEEE Journal of Solid-State Circuits 31(5), 677–688 (1996)
Zhang, C., Asanovic, K.: A way-halting cache for low-energy high-performance systems. ACM Trans. Archit. Code Optim. 2(1) (2005)
Zhu, Z., Zhang, X.: Access-mode predictions for low-power cache design. IEEE Micro. 22(2) (2002)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2009 Springer-Verlag Berlin Heidelberg
About this chapter
Cite this chapter
Keramidas, G., Xekalakis, P., Kaxiras, S. (2009). Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches. In: Stenström, P. (eds) Transactions on High-Performance Embedded Architectures and Compilers II. Lecture Notes in Computer Science, vol 5470. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-00904-4_2
Download citation
DOI: https://doi.org/10.1007/978-3-642-00904-4_2
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-00903-7
Online ISBN: 978-3-642-00904-4
eBook Packages: Computer ScienceComputer Science (R0)