Abstract
Chip Multiprocessors have the potential to deliver significant performance, easily in the Teraflop/s range within a few years. To achieve the full exploitation of this potential, it is crucial to develop adequate models of computation that can guide the optimization of algorithms and of architectures. This talk will present results and open issues along three directions:
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The pipeline of accesses in the memory hierarchy to increase memory bandwidth utilization.
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The network-oblivious approach as a step toward efficient algorithmic portability across chip multiprocessors with different organizations.
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The information-exchange methodology to identify the best partition of chip area between functional units and storage elements, under chip I/O bandwidth constraints.
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© 2009 Springer-Verlag Berlin Heidelberg
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Bilardi, G. (2009). Models for Parallel and Hierarchical On-Chip Computation. In: César, E., et al. Euro-Par 2008 Workshops - Parallel Processing. Euro-Par 2008. Lecture Notes in Computer Science, vol 5415. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-00955-6_16
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DOI: https://doi.org/10.1007/978-3-642-00955-6_16
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-00954-9
Online ISBN: 978-3-642-00955-6
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