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Evaluation of Multicore Processors for Embedded Systems by Parallel Benchmark Program Using OpenMP

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Part of the book series: Lecture Notes in Computer Science ((LNPSE,volume 5568))

Abstract

Recently, multicore technology has been introduced to embedded systems in order to improve performance and reduce power consumption. In the present study, three SMP multicore processors for embedded systems and a multicore processor for a desktop PC are evaluated by the parallel benchmark using OpenMP. The results indicate that, even if the memory performance is low, applications that are not memory-intensive exhibit large speedups by parallelization. The results also indicate a large performance improvement due to parallelization using OpenMP, despite its low cost.

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References

  1. The OpenMP Architecture Review Board: The OpenMP API specification for parallel programming, http://openmp.org/wp/

  2. Free Software Foundation: GCC, the GNU Compiler Collection, http://gcc.gnu.org/

  3. Kaneko, S., et al.: A 600MHz Single-Chip Multiprocessor with 4.8GB/s Internal Shared Pipelined Bus and 512kB Internal Memory. In: International Solid-State Circuits Conference (ISSCC), vol. 1, pp. 254–255 (2003)

    Google Scholar 

  4. ARM Limited: ARM11 MPCore Processor Technical Reference Manual (2006)

    Google Scholar 

  5. ARM Limited: Using a CT11MPCore with the RealView Emulation Baseboard (2006)

    Google Scholar 

  6. Yoshida, Y., et al.: A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption. In: International Solid-State Circuits Conference (ISSCC), pp. 100–590 (2007)

    Google Scholar 

  7. The Linux Kernel Archives, http://kernel.org/

  8. Guthaus, M., et al.: MiBench: A free, commercially representative embedded benchmark suite. In: IEEE 4th Annual Workshop on Workload Characterization (2001)

    Google Scholar 

  9. The Embedded Microprocessor Benchmark Consortium: EEMBC — The Embedded Microprocessor Benchmark Consortium, http://www.eembc.org/

  10. Bailey, D., et al.: The NAS Parallel Benchmarks. RNR Technical Report RNR-94-007, NASA Ames Research Center (1994)

    Google Scholar 

  11. Jin, H., Frumkin, M., Yan, J.: The OpenMP Implementation of NAS Parallel Benchmarks and Its Performance. NAS Technical Report NAS-99-011, NAS System Division NASA Ames Research Center (1999)

    Google Scholar 

  12. Lee, C., Potkonjak, M., Mangione-Smith, H.: MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems. In: International Symposium on Microarchitecture (Micro-30), pp. 330–335 (1997)

    Google Scholar 

  13. Hotta, Y., Sato, M., Nakajima, Y., Ojima, Y.: OpenMP Implementation and Performance on Embedded Renesas M32R Chip Multiprocessor. In: Sixth European Workshop on OpenMP (EWOMP 2004), pp. 37–42 (2004)

    Google Scholar 

  14. Bull, J.M.: Measuring Synchronisation and Scheduling Overheads in OpenMP. In: European Workshop on OpenMP (EWOMP 1999), pp. 99–105 (1999)

    Google Scholar 

  15. Fursin, G., Cavazos, J., O’Boyle, M., Temam, O.: MiDataSets: Creating The Conditions For A More Realistic Evaluation of Iterative Optimization. In: De Bosschere, K., Kaeli, D., Stenström, P., Whalley, D., Ungerer, T. (eds.) HiPEAC 2007. LNCS, vol. 4367, pp. 245–260. Springer, Heidelberg (2007)

    Chapter  Google Scholar 

  16. Blume, H., von Livonius, J., Rotenberg, L., Noll, T.G., Bothe, H., Brakensiek, J.: OpenMP-based parallelization on an MPCore multiprocessor platform - A performance and power analysis. Journal of Systems Architecture 54(11), 1019–1029 (2008)

    Article  Google Scholar 

  17. Seo, H., Kim, S.W.: OpenMP Directive Extension for BlackFin 561 Dual Core Processor. In: Sixth IEEE International Conference on Computer and Information Technology (CIT 2006), p. 49 (2006)

    Google Scholar 

  18. Miyamoto, T., Asaka, S., Mikami, H., Mase, M., Wada, Y., Nakano, H., Kimura, K., Kasahara, H.: Parallelization with Automatic Parallelizing Compiler Generating Consumer Electronics Multicore API. In: International Symposium on Parallel and Distributed Processing with Applications (ISPA 2008), pp. 600–607 (2008)

    Google Scholar 

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© 2009 Springer-Verlag Berlin Heidelberg

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Hanawa, T., Sato, M., Lee, J., Imada, T., Kimura, H., Boku, T. (2009). Evaluation of Multicore Processors for Embedded Systems by Parallel Benchmark Program Using OpenMP. In: Müller, M.S., de Supinski, B.R., Chapman, B.M. (eds) Evolving OpenMP in an Age of Extreme Parallelism. IWOMP 2009. Lecture Notes in Computer Science, vol 5568. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-02303-3_2

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  • DOI: https://doi.org/10.1007/978-3-642-02303-3_2

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-02284-5

  • Online ISBN: 978-3-642-02303-3

  • eBook Packages: Computer ScienceComputer Science (R0)

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