Abstract
This paper discusses the hardware design and implementation of a hand sign recognition system with a simplified discrete Fourier transforms (DFTs) that calculate the magnitude spectrum. Two alternative hardware design solutions that implement the system are proposed. One uses parallel classifier network, the other uses serial one. With the parallel network, the circuit size of the recognition system is over 280,000-gate while the system with the serial classifier network requires about 90,000-gate of hardware resources. Regarding the operating speed, it has been revealed that the operation speed of the both system is quick enough to process NTSC video frame in real time.
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Hikawa, H., Fujimura, H. (2009). Hardware Design of Japanese Hand Sign Recognition System. In: Köppen, M., Kasabov, N., Coghill, G. (eds) Advances in Neuro-Information Processing. ICONIP 2008. Lecture Notes in Computer Science, vol 5507. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-03040-6_102
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DOI: https://doi.org/10.1007/978-3-642-03040-6_102
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-03039-0
Online ISBN: 978-3-642-03040-6
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