Abstract
The reliability of nano-sized combinational circuits can be estimated by using different techniques, such as mathematical equations, Monte Carlo simulations, algorithmic approaches, and combinations of these. Commonly used equations are functions of gate count, and of the reliability and number of devices that make up the gates. The aim of this paper is to present a(n alternative) neural-based approach which is more accurate than applying simple equations, while being faster than the time-consuming Monte Carlo technique.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
International Technology Roadmap for Semiconductors (ITRS). Semiconductor Industry Association, Austin, TX, USA (2007, 2008), http://public.itrs.net/
Forshaw, M.R.B., Nikolic, K., Sadek, A.: ANSWERS: Autonomous Nanoelectronic Systems With Extended Replication and Signaling. University College London, London, UK (2001); MEL-ARI #28667, 3rd Year Annual Report, 1–32 (2001), http://ipga.phys.ucl.ac.uk/research/answers/reports/3rd_year_UCL.pdf
Ibrahim, W., Beg, A., Amer, H.: A Bayesian Based EDA Tool for Accurate VLSI Reliability Evaluations. In: International Conference on Innovations in Information Technology (Innovations 2008), Al-Ain, UAE, pp. 101–105 (2008)
Witten, I.H., Frank., E.: Data Mining. Morgan Kaufmann, New York (2005)
RTL-to-Gates Synthesis Using Synopsys Design Compiler (rev. March 2, 2008), http://csg.csail.mit.edu/6.375/handouts/tutorials/tut4dc.pdf
Rejimon, T., Bhanja, S.: An Accurate Probabilistic Model for Error Detection. In: International Conference on VLSI Design (VLSID 2005), Piscataway, NJ, USA, pp. 717–722 (2005)
Tosun, S., Mansouri, N., Arvas, E., Kandemir, M., Xie, Y., Hung, W.L.: Reliability-Centric Hardware/Software Co-Design. In: International Symposium on Quality of Electronic Design (ISQED 2005), pp. 375–380. IEEE Computer Society, Los Alamitos (2005)
Gilson, I.W., Ivandro, R., Michele, G.V., Kastensmidt, F.G.L.: Single Event Transients in Dynamic Logic. In: Annual Symposium on Integrated Circuits and Systems Design, pp. 184–189. ACM, Ouro Preto (2006)
Li, H., Mundy, J., Patterson, W., Kazazis, D., Zaslavsky, A., Bahar, R.I.: A Model for Soft Errors in the Subthreshold CMOS Inverter. In: Workshop on System Effects of Logic Soft Errors (SELSE-2), Urbana-Champaign, IL, USA (2006)
Beg, A., Ibrahim, W.: On Teaching Circuit Reliability. In: Frontiers in Education Conference (FIE 2008), Saratoga Springs, NY, USA, pp. T3H12- T3H17 (2008)
Beg, A., Ibrahim, W.: Relating Reliability to Circuit Topology. In: North Eastern Workshop on Circuits and Systems (NEWCAS 2009), Toulouse, France (2009) (in press)
Ibrahim, W., Beiu, V.: A Bayesian–based EDA Tool for nano-Circuits Reliability Calculations. In: International ICST Conference on Nano-Networks (Nano-Net 2009), Luzern, Switzerland (2009) (in press)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2009 ICST Institute for Computer Science, Social Informatics and Telecommunications Engineering
About this paper
Cite this paper
Beg, A. (2009). Improving Nano-circuit Reliability Estimates by Using Neural Methods. In: Schmid, A., Goel, S., Wang, W., Beiu, V., Carrara, S. (eds) Nano-Net. NanoNet 2009. Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, vol 20. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-04850-0_35
Download citation
DOI: https://doi.org/10.1007/978-3-642-04850-0_35
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-04849-4
Online ISBN: 978-3-642-04850-0
eBook Packages: Computer ScienceComputer Science (R0)