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International Conference on Nano-Networks

NanoNet 2009: Nano-Net pp 276–284Cite as

A Bayesian-Based EDA Tool for Nano-circuits Reliability Calculations

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Abstract

As the sizes of (nano-)devices are aggressively scaled deep into the nanometer range, the design and manufacturing of future (nano-)circuits will become extremely complex and inevitably will introduce more defects while their functioning will be adversely affected by transient faults. Therefore, accurately calculating the reliability of future designs will become a very important aspect for (nano-)circuit designers as they investigate several design alternatives to optimize the trade-offs between the conflicting metrics of area-power-energy-delay versus reliability. This paper introduces a novel generic technique for the accurate calculation of the reliability of future nano-circuits. Our aim is to provide both educational and research institutions (as well as the semiconductor industry at a later stage) with an accurate and easy to use tool for closely comparing the reliability of different design alternatives, and for being able to easily select the design that best fits a set of given (design) constraints. Moreover, the reliability model generated by the tool should empower designers with the unique opportunity of understanding the influence individual gates play on the design’s overall reliability, and identifying those (few) gates which impact the design’s reliability most significantly.

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Author information

Authors and Affiliations

  1. College of Information Technology, UAE University, P.O. Box 17551, Al Ain, UAE

    Walid Ibrahim & Valeriu Beiu

Authors
  1. Walid Ibrahim
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  2. Valeriu Beiu
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Editor information

Editors and Affiliations

  1. Microelectronic Systems Laboratory STI-LSM, Swiss Federal Institute of Technology EPFL, ELD339 Btiment ELD, Station 11, 1015, Lausanne, Switzerland

    Alexandre Schmid

  2. Business Administration, State University of New York,, 310b, 1400 Washington Ave.,, 12222, Albany, NY, USA

    Sanjay Goel

  3. College of Nanoscale Science and Engineering, University of Albany, 12222, Albany, NY, USA

    Wei Wang

  4. College of Information Technology, UAE University, P.O. Box 17555, Al Ain, Abu Dhabi, United Arab Emirates

    Valeriu Beiu

  5. Lausanne EPFL IC ISIM LSI1 INF 333 (Btment INF) Station 14, Swiss Federal Institute of Technology, CH-1015, Lausanne, Switzerland

    Sandro Carrara

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© 2009 ICST Institute for Computer Science, Social Informatics and Telecommunications Engineering

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Ibrahim, W., Beiu, V. (2009). A Bayesian-Based EDA Tool for Nano-circuits Reliability Calculations. In: Schmid, A., Goel, S., Wang, W., Beiu, V., Carrara, S. (eds) Nano-Net. NanoNet 2009. Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, vol 20. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-04850-0_36

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  • DOI: https://doi.org/10.1007/978-3-642-04850-0_36

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-04849-4

  • Online ISBN: 978-3-642-04850-0

  • eBook Packages: Computer ScienceComputer Science (R0)

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