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Speculation for Parallelizing Runtime Checks

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Stabilization, Safety, and Security of Distributed Systems (SSS 2009)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 5873))

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Abstract

We present and evaluate a framework, ParExC, to reduce the runtime penalties of compiler generated runtime checks. An obvious approach is to use idle cores of modern multi-core CPUs to parallelize the runtime checks. This could be accomplished by (a) parallelizing the application and in this way, implicitly parallelizing the checks, or (b) by parallelizing the checks only. Parallelizing an application is rarely easy and frameworks that simplify the parallelization, e.g., like software transactional memory (STM), can introduce considerable overhead. ParExC is based on alternative (b). We compare it with an approach using a transactional memory-based alternative. Our experience shows that ParExC is not only more efficient than the STM-based solution but the manual effort for an application developer to integrate ParExC is lower. ParExC has – in contrast to similar frameworks – two noteworthy features that permit a more efficient parallelization of checks: (1) speculative variables, and (2) the ability to add checks by static instrumentation.

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References

  1. Ruwase, O., Lam, M.S.: A practical dynamic buffer overflow detector. In: NDSS. The Internet Society (2004)

    Google Scholar 

  2. Castro, M., Costa, M., Harris, T.: Securing software by enforcing data-flow integrity. In: OSDI 2006: Proceedings of the 7th symposium on Operating systems design and implementation, Berkeley, CA, USA. USENIX Association (2006)

    Google Scholar 

  3. Borkar, S.: Designing reliable systems from unreliable components: The challenges of transistor variability and degradation. IEEE Micro. (2005)

    Google Scholar 

  4. Oh, N., Mitra, S., McCluskey, E.J.: ED4I: Error detection by diverse data and duplicated instructions. IEEE Trans. Comput. 51 (2002)

    Google Scholar 

  5. Nightingale, E.B., Peek, D., Chen, P.M., Flinn, J.: Parallelizing security checks on commodity hardware. SIGARCH Comput. Archit. News 36(1), 308–318 (2008)

    Article  Google Scholar 

  6. Newsome, J., Song, D.: Dynamic taint analysis for automatic detection, analysis, and signature generation of exploits on commodity software. In: Proceedings of the Network and Distributed System Security Symposium (2005)

    Google Scholar 

  7. Xu, W., Bhatkar, S., Sekar, R.: Taint-enhanced policy enforcement: a practical approach to defeat a wide range of attacks. In: Proceedings of the 15th USENIX Security Symposium, Berkeley, CA, USA. USENIX Association (2006)

    Google Scholar 

  8. Felber, P., Fetzer, C., Riegel, T.: Dynamic performance tuning of word-based software transactional memory. In: Proceedings of the 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPoPP (2008)

    Google Scholar 

  9. Ruwase, O., Gibbons, P.B., Mowry, T.C., Ramachandran, V., Chen, S., Kozuch, M., Ryan, M.: Parallelizing dynamic information flow tracking. In: Proceedings of the 20th annual symposium on Parallelism in Algorithms and Architectures (SPAA), USA. ACM Press, New York (2008)

    Google Scholar 

  10. Schiffel, U., Süßkraut, M., Fetzer, C.: An-encoding compiler: Building safety-critical systems with commodity hardware. In: The 28th International Conference on Computer Safety, Reliability and Security, SafeComp 2009 (2009)

    Google Scholar 

  11. Lattner, C., Adve, V.: LLVM: A Compilation Framework for Lifelong Program Analysis & Transformation. In: Proceedings of the 2004 International Symposium on Code Generation and Optimization (CGO 2004), California (2004)

    Google Scholar 

  12. Felber, P., Fetzer, C., Müller, U., Riegel, T., Süßkraut, M., Sturzrehm, H.: Transactifying applications using an open compiler framework. In: TRANSACT (2007)

    Google Scholar 

  13. Cao Minh, C., Chung, J., Kozyrakis, C., Olukotun, K.: Stamp: Stanford transactional applications for multi-processing. In: IISWC 2008: Proceedings of The IEEE International Symposium on Workload Characterization (September 2008)

    Google Scholar 

  14. Wallace, S., Hazelwood, K.: Superpin: Parallelizing dynamic instrumentation for real-time performance. In: 5th Annual International Symposium on Code Generation and Optimization, San Jose, CA, March 2007, pp. 209–217 (2007)

    Google Scholar 

  15. Zilles, C., Sohi, G.: Master/slave speculative parallelization. In: MICRO 35: Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, pp. 85–96. IEEE Computer Society Press, Los Alamitos (2002)

    Google Scholar 

  16. Kelsey, K., Bai, T., Ding, C., Zhang, C.: Fast track: A software system for speculative program optimization. In: CGO 2009: Proceedings of the 2009 International Symposium on Code Generation and Optimization, Washington, DC, USA, pp. 157–168. IEEE Computer Society Press, Los Alamitos (2009)

    Chapter  Google Scholar 

  17. Olukotun, K., Hammond, L., Willey, M.: Improving the performance of speculatively parallel applications on the hydra cmp. In: ICS 1999: Proceedings of the 13th international conference on Supercomputing, USA. ACM Press, New York (1999)

    Google Scholar 

  18. Steffan, J.G., Colohan, C.B., Zhai, A., Mowry, T.C.: A scalable approach to thread-level speculation. SIGARCH Comput. Archit. News 28(2), 1–12 (2000)

    Article  Google Scholar 

  19. Steffan, J.G., Colohan, C.B., Zhai, A., Mowry, T.C.: Improving value communication for thread-level speculation. In: HPCA 2002: Proceedings of the 8th International Symposium on High-Performance Computer Architecture, Washington, DC, USA, p. 65. IEEE Computer Society Press, Los Alamitos (2002)

    Google Scholar 

  20. Pickett, C.J.F., Verbrugge, C.: Return value prediction in a Java virtual machine. In: Proceedings of the Second Value-Prediction and Value-Based Optimization Workshop (VPW2), October 2004, pp. 40–47 (2004)

    Google Scholar 

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Süßkraut, M. et al. (2009). Speculation for Parallelizing Runtime Checks. In: Guerraoui, R., Petit, F. (eds) Stabilization, Safety, and Security of Distributed Systems. SSS 2009. Lecture Notes in Computer Science, vol 5873. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-05118-0_48

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  • DOI: https://doi.org/10.1007/978-3-642-05118-0_48

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-05117-3

  • Online ISBN: 978-3-642-05118-0

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