Abstract
This talk will describe a many-core visual computing architecture code named Larrabee. Larrabee uses multiple in-order x86 CPU cores that are augmented by a wide vector processor unit, as well as some fixed function logic blocks. The talk will go into an overview of the Larrabee architecture and will cover the LRB Vector ISA in detail. We’ll then cover the Larrabee programming model and finally close with how one would target Larrabee for high performance 3D graphics.
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© 2010 Springer-Verlag Berlin Heidelberg
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Espasa, R. (2010). Larrabee: A Many-Core Intel Architecture for Visual Computing. In: Patt, Y.N., Foglia, P., Duesterwald, E., Faraboschi, P., Martorell, X. (eds) High Performance Embedded Architectures and Compilers. HiPEAC 2010. Lecture Notes in Computer Science, vol 5952. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-11515-8_2
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DOI: https://doi.org/10.1007/978-3-642-11515-8_2
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-11514-1
Online ISBN: 978-3-642-11515-8
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