Abstract
This paper reports a 0.5V bulk PMOS dynamic-threshold technique enhanced with dual threshold (MTCMOS): BP-DTMOS-DT for design optimization of low-power SOC application using 90nm multi-threshold CMOS technology. Via the HVT/BP-DTMOS-DT-type logic cell technique generated by the special gate-level dual-threshold static power optimization methodology (GDSPOM) procedure, a 0.5V 16-bit multiplier circuit has been designed and optimized, consuming 22% less static leakage power at the operating frequency of 400MHz as compared to the HVT/LVT-type counterpart optimized by the GDSPOM reported before.
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Lin, CH., Kuo, J.B. (2010). Design Optimization of Low-Power 90nm CMOS SOC Application Using 0.5V Bulk PMOS Dynamic-Threshold with Dual Threshold (MTCMOS): BP-DTMOS-DT Technique. In: Monteiro, J., van Leuken, R. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2009. Lecture Notes in Computer Science, vol 5953. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-11802-9_17
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DOI: https://doi.org/10.1007/978-3-642-11802-9_17
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-11801-2
Online ISBN: 978-3-642-11802-9
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