Skip to main content

Practical Design Space Exploration of an H264 Decoder for Handheld Devices Using a Virtual Platform

  • Conference paper

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 5953))

Abstract

H264 is a promising standard for mobile appliances since it allows to play on the tradeoff between data transmission rates and processing needs. This tradeoff is a common issue in mobile appliance design as it leaves space for power savings. We propose here a virtual platform based global approach, i.e. investigating hardware solutions, software solutions and both, to define a set of energy-optimized degraded operating modes for a H264 decoder software. Results of this exploration show that reasonable energy savings for degraded modes can be achieved without loosing too much image quality.

This is a preview of subscription content, log in via an institution.

Buying options

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Baker, M.A., Parameswaran, V., Chatha, K.S., Li, B.: Power reduction via macroblock prioritization for power aware h.264 video applications. In: CODES/ISSS 2008: Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis, pp. 261–266. ACM, New York (2008)

    Chapter  Google Scholar 

  2. Bellard, F.: QEMU, a Fast and Portable Dynamic Translator. In: USENIX 2005 Annual Technical Conference, FREENIX Track, pp. 41–46 (2005)

    Google Scholar 

  3. Coppola, M., Grammatikakis, M., Locatelli, R., Maruccia, G., Pieralisi, L., Mafie, F.: System-on-chip design and technologies. In: Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC, p. 288. CRC Press, Boca Raton (2008)

    Google Scholar 

  4. Gligor, M., Fournel, N., Pétrot, F.: Using binary translation in event driven simulation for fast and flexible mpsoc simulation. In: 7th IEEE/ACM International Conference on Hardware/Software-Co-Design and System Synthesis, Grenoble, France, October 2009, pp. 71–80 (2009)

    Google Scholar 

  5. Hommais, D., Pétrot, F.: Efficient combinational loops handling for cycle precise simulation of system on a chip. In: Proceedings of the 24th Euromicro Conference, Vesteras, Sweden, vol. 1, pp. 51–54 (1998)

    Google Scholar 

  6. Horowitz, M., Joch, A., Kossentini, F., Hallapuro, A.: H.264/avc baseline profile decoder complexity analysis. IEEE Transactions on Circuits and Systems for Video Technology 13(7), 704–716 (2003)

    Article  Google Scholar 

  7. Li, L., Goto, S., Ikenaga, T.: An efficient deblocking filter architecture with 2-dimensional parallel memory for h.264/avc. In: ASP-DAC 2005: Proceedings of the 2005 conference on Asia South Pacific design automation, pp. 623–626. ACM, New York (2005)

    Chapter  Google Scholar 

  8. Mihocka, D., Shwartsman, S.: Virtualization without direct execution - designing a portable vm. In: 1st Workshop on Architectural and Microarchitectural Support for Binary Translation, ISCA35 (2008)

    Google Scholar 

  9. Peng, H.-K., Lee, C.-H., Chen, J.-W., Lo, T.-J., Chang, Y.-H., Hsu, S.-T., Lin, Y.-C., Chao, P., Hung, W.-C., Jan, K.-Y.: A highly integrated 8mw h.264/avc main profile real-time cif video decoder on a 16mhz soc platform. In: ASP-DAC 2007: Proceedings of the 2007 conference on Asia South Pacific design automation, Washington, DC, USA, pp. 112–113. IEEE Computer Society, Los Alamitos (2007)

    Google Scholar 

  10. Roitzsch, M.: Slice-balancing h.264 video encoding for improved scalability of multicore decoding. In: EMSOFT 2007: Proceedings of the 7th ACM & IEEE international conference on Embedded software, pp. 269–278. ACM, New York (2007)

    Chapter  Google Scholar 

  11. Stitt, G., Vahid, F., McGregor, G., Einloth, B.: Hardware/software partitioning of software binaries: a case study of h.264 decode. In: CODES+ISSS 2005: Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, pp. 285–290. ACM, New York (2005)

    Chapter  Google Scholar 

  12. SystemC, http://www.systemc.org/

  13. Xu, K., Choy, C.S.: Low-power h.264/avc baseline decoder for portable applications. In: ISLPED 2007: Proceedings of the 2007 international symposium on Low power electronics and design, pp. 256–261. ACM, New York (2007)

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2010 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Gligor, M. et al. (2010). Practical Design Space Exploration of an H264 Decoder for Handheld Devices Using a Virtual Platform. In: Monteiro, J., van Leuken, R. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2009. Lecture Notes in Computer Science, vol 5953. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-11802-9_25

Download citation

  • DOI: https://doi.org/10.1007/978-3-642-11802-9_25

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-11801-2

  • Online ISBN: 978-3-642-11802-9

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics