Abstract
The approaches to self-timed hardware design are presented. The conditions of intersystem integration of synchronous and self-timed devices are considered through the example of the quasi-delay-insensitive computing device development. This device performs functions of division and square root extraction. It operates with numbers of single and double precisions corresponding to the IEEE 754 standard.
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Stepchenkov, Y., Diachenko, Y., Zakharov, V., Rogdestvenski, Y., Morozov, N., Stepchenkov, D. (2010). Quasi-Delay-Insensitive Computing Device: Methodological Aspects and Practical Implementation. In: Monteiro, J., van Leuken, R. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2009. Lecture Notes in Computer Science, vol 5953. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-11802-9_32
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DOI: https://doi.org/10.1007/978-3-642-11802-9_32
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