Abstract
This paper investigates the residue arithmetic as a solution for the design of variation-tolerant circuits. Motivated by the modular organization of residue processors, we comparatively study the sensitivity of residue arithmetic-based and binary processors to delay variations, and in particular the impact of delay variations onto the maximum critical path. Experiments are performed on two multiply-add (MAC) circuits based on residue and binary arithmetic. Results reveal that residue arithmetic-based circuits are up to 94% less sensitive to delay variation than binary circuits, thus leading to increased timing yield.
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Kouretas, I., Paliouras, V. (2010). Residue Arithmetic for Variation-Tolerant Design of Multiply-Add Units. In: Monteiro, J., van Leuken, R. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2009. Lecture Notes in Computer Science, vol 5953. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-11802-9_7
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DOI: https://doi.org/10.1007/978-3-642-11802-9_7
Publisher Name: Springer, Berlin, Heidelberg
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