Abstract
FPGA implementation of MGS-QRD is presented in this paper. Mapping conventional QR triangular array of (2m 2+3m+1) cells onto a linear architecture of m+1 cells is employed to reduce the number of required QR processors. The architecture for MGS-QRD implementation is discussed, including the structure of a boundary cell (BC) and internal cell (IC). A divider in BC is modified as a Look-Up Table (LUT) and multiplier. The multiplier divided from the divider can be accomplished by sharing it with another multiplier to reduce the resource for BC implementation. Furthermore, the conventional complex multiplication in IC is also modified with three multipliers and four adders. The designed architecture based on discrete mapping of MGS-QRD is implemented to examine FPGA resource utilization. The implementation results show the FPGA performance and resource utilization of MGS-QRD.
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References
Gesbert, D., Shafi, M., Shiu, D., Smith, P.J., Naguib, A.: From Theory to Practice: An Overview of MIMO Space-Time Coded Wireless Systems. IEEE Journal on Selec. Areas in Commu. 21(3), 281–302 (2003)
El-Amawy, A., Dharmarajan, K.R.: Parallel VLSI Algorithm for Stable Inversion of dense matrics. IEEE Proceeding on Computer and Digital Technique 136(6), 60–75 (2005)
Golub, G.H., Van Loan, C.F.: Matrix Computation. Johns Hopkins, New York (1996)
Bjork, A.: Numerical Methods for Least Square Problem. AP-SIAM, Philadelphia (1996)
Sing, C.K., Prasad, S.H., Balsara, P.T.: A Fixed-point Implementation for QR Decomposition. In: IEEE Proceeding Dallas Workshop Circuits Systems, pp. 75–78 (2006)
Lightbody, G., Woods, R., Walke, R.: Design of a Parameterizable Silicon Intellectual Property Core for QR-Based RLS Filtering. IEEE Trans. on very large scale integration (VLSI) systems 11(4), 659–678 (2003)
Lightbody, G., Walke, R., Woods, R., McCanny, J.: Novel mapping of a linear QR architecture. In: ICASSP 1999, pp. 1933–1936 (1999)
Lin, K., Lin, C., Chang, R.C., Huang, C., Chen, F.: Iterative QR Decomposition Architecture Using the Modified Gram-Schmidt Algorithm. In: ISCAS 2009, pp. 1409–1412 (2009)
Benhamid, M., Othman, M.: FPGA Implementation of a Canonical Signed Digit Multiplier-less based FFT Processor for Wireless Communication Applications. In: ICSE 2006, pp. 641–645 (2006)
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Boonpoonga, A., Janyavilas, S., Sirisuk, P., Krairiksh, M. (2010). FPGA Implementation of QR Decomposition Using MGS Algorithm. In: Sirisuk, P., Morgan, F., El-Ghazawi, T., Amano, H. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2010. Lecture Notes in Computer Science, vol 5992. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-12133-3_39
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DOI: https://doi.org/10.1007/978-3-642-12133-3_39
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