Abstract
The High leakage current in deep sub-micrometer region is becoming a significant contributor to power dissipation in CMOS circuits as threshold voltage, channel length, and the gate oxide thickness are reduced. As the standby current in memories is critical in low-power design. By lowering the supply voltage (VDD) to its standby limit, the data retention voltage (DRV), SRAM leakage power can be reduced substantially. The DRV increases with transistor mismatches. In this paper, we demonstrated the drowsy cache technique which shows a decrease in the leakage current dissipation in deep sub-micron designs of memory cells and embedded memories. The focus of this work is to simulate an effective scheme for SRAM leakage suppression in battery-powered mobile applications.
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Shukla, N.K., Birla, S., Singh, R.K. (2010). Analysis and Simulation of a Low Leakage Conventional SRAM Memory Cell at Deep Sub-micron Level. In: Das, V.V., et al. Information Processing and Management. BAIP 2010. Communications in Computer and Information Science, vol 70. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-12214-9_108
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DOI: https://doi.org/10.1007/978-3-642-12214-9_108
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