Abstract
Power efficiency in VLSI design is in prime focus in today’s state of the art. A simple method of reducing power consumption in cache memories and other logic is presented here. We make use of both edges of clock signals to perform cache accesses in order to enable the reduction of operating frequency - and thus, dynamic power - without affecting performance to a large extent. Experimental results are presented, making use of the OpenSPARC T1 and Alpha AXP 21064 processor caches.
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References
Zhang, C.: An Efficient Direct Mapped Instruction Cache for Application-Specific Embedded Systems, Jersey City, New Jersey, USA (2005)
Megalingam, R.K., Krishnan, N., Arjun Ashok, V., Arunkumar, M.: Highly Power Efficient, Uncompromised Performance Cache Design Using Dual-Edged Clock. In: 2nd IEEE ICCSIT 2009, Beijing, China (2009)
Weste, H., Eshraghian, K.: Principles of CMOS VLSI Design
Kang, S.-M., Leblebici, Y.: CMOS Digital Integrated Circuits, 3rd edn. Tata McGraw-Hill, New York (2003)
Mano, M.: Computer System Architecture, 3rd edn.
Sun Microsystems: OpenSPARC T1 Microarchitecture Specification (2006)
OpenSPARC, http://www.opensparc.net/
Xilinx, http://www.xilinx.com/
Hennessy, J.L., Patterson, D.A.: Computer Organization and Design – The Hardware-Software Interface. Morgan Kaufman, San Francisco (1997)
Mathur, A., Wang, Q., Dimri, V.: Power Reduction Techniques at the RTL and System Level. In: 22nd International Conference on VLSI Design, January 5-9 (2009)
Tirumalashetty, V., Mahmoodi, H.: Clock Gating and Negative Edge Triggering for Energy Recovery Clock (2007)
Abella, J., González, A.: Power Efficient Data Cache Designs. In: Proceedings of the 21st International Conference on Computer Design, ICCD 2003 (2003)
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Kannan, M.R., Arunkumar, M., Ashok, V.A., Nived, K., Daniel, C.J. (2010). Power-Efficient Cache Design Using Dual-Edge Clocking Scheme in Sun OpenSPARC T1 and Alpha AXP Processors. In: Das, V.V., et al. Information Processing and Management. BAIP 2010. Communications in Computer and Information Science, vol 70. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-12214-9_19
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DOI: https://doi.org/10.1007/978-3-642-12214-9_19
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-12213-2
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